Re: [PATCH v3 0/6] target/riscv: Add support for Control Transfer Records Ext.

[Rajnesh Kanwal <rkanwal@rivosinc.com>]

On Tue, Nov 5, 2024 at 3:58 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 11/4/24 21:51, Rajnesh Kanwal wrote:
> >   target/riscv/cpu.c                             |  26 ++-
> >   target/riscv/cpu.h                             |  13 ++
> >   target/riscv/cpu_bits.h                        |  94 ++++++++
> >   target/riscv/cpu_cfg.h                         |   2 +
> >   target/riscv/cpu_helper.c                      | 266 ++++++++++++++++++++++
> >   target/riscv/csr.c                             | 294 ++++++++++++++++++++++++-
> >   target/riscv/helper.h                          |   9 +-
> >   target/riscv/insn32.decode                     |   2 +-
> >   target/riscv/insn_trans/trans_privileged.c.inc |  22 +-
> >   target/riscv/insn_trans/trans_rvi.c.inc        |  31 +++
> >   target/riscv/insn_trans/trans_rvzce.c.inc      |  20 ++
> >   target/riscv/op_helper.c                       | 155 ++++++++++++-
> >   target/riscv/tcg/tcg-cpu.c                     |  11 +
> >   target/riscv/translate.c                       |  10 +
> >   14 files changed, 941 insertions(+), 14 deletions(-)
>
> You're missing code in machine.c to migrate the new state.
>

Nice catch. Thanks for your feedback Richard. I have fixed
all your feedback in v4.

- Rajnesh

>
> r~