From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <alistair23@gmail.com>
Subject: Re: [PATCH v5 04/11] target/riscv: Don't set PMP feature in the cpu init
Date: Mon, 1 Jun 2020 13:26:09 +0800 [thread overview]
Message-ID: <CAEUhbmU5hsKCunoEs4tqh4_LaSN+xcfCm1u3aHzf5WbY03feGg@mail.gmail.com> (raw)
In-Reply-To: <a1bd144a1fe3e80a9b512edfe602c9a32e697429.1590704015.git.alistair.francis@wdc.com>
On Fri, May 29, 2020 at 6:22 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> The PMP is enabled by default via the "pmp" property so there is no need
> for us to set it in the init function. As all CPUs have PMP support just
> remove the set_feature() call in the CPU init functions.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 7 -------
> 1 file changed, 7 deletions(-)
>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
next prev parent reply other threads:[~2020-06-01 5:27 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-28 22:14 [PATCH v5 00/11] RISC-V Add the OpenTitan Machine Alistair Francis
2020-05-28 22:14 ` [PATCH v5 01/11] riscv/boot: Add a missing header include Alistair Francis
2020-05-28 22:14 ` [PATCH v5 02/11] target/riscv: Don't overwrite the reset vector Alistair Francis
2020-05-28 22:14 ` [PATCH v5 03/11] target/riscv: Disable the MMU correctly Alistair Francis
2020-06-01 5:24 ` Bin Meng
2020-05-28 22:14 ` [PATCH v5 04/11] target/riscv: Don't set PMP feature in the cpu init Alistair Francis
2020-06-01 5:26 ` Bin Meng [this message]
2020-05-28 22:14 ` [PATCH v5 05/11] target/riscv: Add the lowRISC Ibex CPU Alistair Francis
2020-05-28 22:14 ` [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine Alistair Francis
2020-06-09 13:48 ` Damien Hedde
2020-06-09 14:21 ` Philippe Mathieu-Daudé
2020-06-09 23:09 ` Alistair Francis
2020-09-08 14:52 ` Peter Maydell
2020-09-09 17:49 ` Alistair Francis
2020-09-09 19:00 ` Peter Maydell
2020-09-09 19:51 ` Palmer Dabbelt
2020-09-10 18:48 ` Alistair Francis
2023-05-19 17:15 ` [PATCH v5 6/11] " Philippe Mathieu-Daudé
2020-05-28 22:14 ` [PATCH v5 07/11] hw/char: Initial commit of Ibex UART Alistair Francis
2020-06-01 21:23 ` Alistair Francis
2020-06-02 11:22 ` LIU Zhiwei
2020-06-02 12:28 ` LIU Zhiwei
2020-06-02 17:54 ` Alistair Francis
2020-06-03 10:33 ` LIU Zhiwei
2020-06-03 15:56 ` Alistair Francis
2020-06-04 1:59 ` LIU Zhiwei
2020-06-04 4:35 ` Alistair Francis
2020-06-04 5:05 ` LIU Zhiwei
2020-06-04 5:46 ` Alistair Francis
2020-06-04 5:40 ` LIU Zhiwei
2020-06-02 17:46 ` Alistair Francis
2020-05-28 22:14 ` [PATCH v5 08/11] hw/intc: Initial commit of lowRISC Ibex PLIC Alistair Francis
2020-05-28 22:14 ` [PATCH v5 09/11] riscv/opentitan: Connect the PLIC device Alistair Francis
2020-05-28 22:14 ` [PATCH v5 10/11] riscv/opentitan: Connect the UART device Alistair Francis
2020-05-28 22:14 ` [PATCH v5 11/11] target/riscv: Use a smaller guess size for no-MMU PMP Alistair Francis
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