From: Bin Meng <bmeng.cn@gmail.com>
To: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <alistair23@gmail.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v7 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine
Date: Fri, 6 Sep 2019 08:32:24 +0800 [thread overview]
Message-ID: <CAEUhbmUvn-4DqLXZrz-DPDibRdfnd7ZmMHkfwSqieGeLj9XiGg@mail.gmail.com> (raw)
In-Reply-To: <mhng-1e0d1887-7084-4997-bcc4-a254d05f629a@palmer-si-x1e>
Hi Palmer,
On Fri, Sep 6, 2019 at 3:00 AM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Thu, 05 Sep 2019 08:25:46 PDT (-0700), bmeng.cn@gmail.com wrote:
> > Hi Alistair,
> >
> > On Thu, Sep 5, 2019 at 3:50 AM Alistair Francis <alistair23@gmail.com> wrote:
> >>
> >> On Sat, Aug 31, 2019 at 7:54 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >> >
> >> > As of today, the QEMU 'sifive_u' machine is a special target that does
> >> > not boot the upstream OpenSBI/U-Boot firmware images built for the real
> >> > SiFive HiFive Unleashed board. Hence OpenSBI supports a special platform
> >> > "qemu/sifive_u". For U-Boot, the sifive_fu540_defconfig is referenced
> >> > in the OpenSBI doc as its payload, but that does not boot at all due
> >> > to various issues in current QEMU 'sifive_u' machine codes.
> >> >
> >> > This series aims to improve the emulation fidelity of sifive_u machine,
> >> > so that the upstream OpenSBI, U-Boot and kernel images built for the
> >> > SiFive HiFive Unleashed board can be used out of the box without any
> >> > special hack.
> >> >
> >> > The major changes include:
> >> > - Heterogeneous harts creation supported, so that we can create a CPU
> >> > that exactly mirrors the real hardware: 1 E51 + 4 U54.
> >> > - Implemented a PRCI model for FU540
> >> > - Implemented an OTP model for FU540, primarily used for storing serial
> >> > number of the board
> >> > - Fixed GEM support that was seriously broken on sifive_u
> >> > - Synced device tree with upstream Linux kernel on sifive_u
> >> >
> >> > OpenSBI v0.4 image built for sifive/fu540 is included as the default
> >> > bios image for 'sifive_u' machine.
> >> >
> >> > The series is tested against OpenSBI v0.4 image for sifive/fu540
> >> > paltform, U-Boot v2019.10-rc1 image for sifive_fu540_defconfig,
> >> > and Linux kernel v5.3-rc3 image with the following patch:
> >> >
> >> > macb: Update compatibility string for SiFive FU540-C000 [1]
> >> >
> >> > OpenSBI + U-Boot, ping/tftpboot with U-Boot MACB driver works well.
> >> > Boot Linux 64-bit defconfig image, verified that system console on
> >> > the serial 0 and ping host work pretty well.
> >> >
> >> > An OpenSBI patch [2] was sent to drop the special "qemu/sifive_u" platform
> >> > support in OpenSBI. The original plan was to get the drop patch applied
> >> > after this QEMU series is merged. However after discussion in the OpenSBI
> >> > mailing list, it seems the best option for us is to let OpenSBI continue
> >> > shipping the special "qemu/sifive_u" platform support to work with QEMU
> >> > version <= 4.1 and deprecate the support sometime in the future. A patch
> >> > will need to be sent to OpenSBI mailing list to update its document.
> >> >
> >> > v4 is now rebased on Palmer's QEMU RISC-V repo "for-master" branch.
> >> > Dropped the following v3 patch that was already done by someone else.
> >> > - riscv: sifive_u: Generate an aliases node in the device tree
> >> > - riscv: sifive_u: Support loading initramfs
> >>
> >> I'm having trouble applying this. Do you mind sharing a public git branch?
> >
> > So I see Palmer has rebased his "for-master" branch against QEMU
> > master and now this patch series cannot be applied cleanly.
> >
> > Even worse, the current "for-master" branch has build errors for QEMU RISC-V.
>
> Sorry, I haven't gotten around to fixing up the patch queue for now. It's
> always OK to just send stuff against Peter's master, particularly if it's a big
> patch set like this, as that's more likely to be a stable base for testing.
I was originally using Peter's branch but later I got to know there
was some patch conflicts between my patch series and what was already
applied in the RISC-V queue. Hence I switched to rebase my series on
"for-master" since v4.
I will rebase my patch series again, and send out a v8 (hopefully the
last version) soon.
Regards,
Bin
prev parent reply other threads:[~2019-09-06 0:34 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-01 2:52 [Qemu-devel] [PATCH v7 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 01/30] riscv: hw: Remove superfluous "linux, phandle" property Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 02/30] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 03/30] riscv: hw: Remove not needed PLIC properties in device tree Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 04/30] riscv: hw: Change create_fdt() to return void Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 07/30] riscv: roms: Remove executable attribute of opensbi images Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 08/30] riscv: sifive_u: Remove the unnecessary include of prci header Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 11/30] riscv: sifive_e: prci: Update the PRCI register block size Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 12/30] riscv: sifive_e: Drop sifive_mmio_emulate() Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 14/30] riscv: hart: Extract hart realize to a separate routine Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array Bin Meng
2019-09-03 23:09 ` Alistair Francis
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 16/30] riscv: sifive_u: Set the minimum number of cpus to 2 Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 17/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 18/30] riscv: sifive_u: Update PLIC hart topology configuration string Bin Meng
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 19/30] riscv: sifive: Implement PRCI model for FU540 Bin Meng
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes Bin Meng
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 21/30] riscv: sifive_u: Add PRCI block to the SoC Bin Meng
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes Bin Meng
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 23/30] riscv: sifive_u: Update UART base addresses and IRQs Bin Meng
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 24/30] riscv: sifive_u: Change UART node name in device tree Bin Meng
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 25/30] riscv: roms: Update default bios for sifive_u machine Bin Meng
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP Bin Meng
2019-09-04 16:37 ` Alistair Francis
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 27/30] riscv: sifive_u: Instantiate OTP memory with a serial number Bin Meng
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 28/30] riscv: sifive_u: Fix broken GEM support Bin Meng
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Bin Meng
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 30/30] riscv: sifive_u: Update model and compatible strings in device tree Bin Meng
2019-09-04 19:49 ` [Qemu-devel] [PATCH v7 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Alistair Francis
2019-09-05 15:25 ` Bin Meng
2019-09-05 19:00 ` Palmer Dabbelt
2019-09-06 0:32 ` Bin Meng [this message]
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