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Wed, 17 Mar 2021 18:58:36 -0700 (PDT) MIME-Version: 1.0 References: <685a79eb7992d8b780570501cdb784b607144f02.1616002766.git.alistair.francis@wdc.com> In-Reply-To: <685a79eb7992d8b780570501cdb784b607144f02.1616002766.git.alistair.francis@wdc.com> From: Bin Meng Date: Thu, 18 Mar 2021 09:58:25 +0800 Message-ID: Subject: Re: [PATCH v1 1/5] target/riscv: Convert the RISC-V exceptions to an enum To: Alistair Francis Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::b35; envelope-from=bmeng.cn@gmail.com; helo=mail-yb1-xb35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , "open list:RISC-V" , "qemu-devel@nongnu.org Developers" , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Mar 18, 2021 at 1:41 AM Alistair Francis wrote: > > Signed-off-by: Alistair Francis > --- > target/riscv/cpu_bits.h | 44 ++++++++++++++++++++------------------- > target/riscv/cpu.c | 2 +- > target/riscv/cpu_helper.c | 4 ++-- > 3 files changed, 26 insertions(+), 24 deletions(-) > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index caf4599207..8ae404c32a 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -527,27 +527,29 @@ > #define DEFAULT_RSTVEC 0x1000 > > /* Exception causes */ > -#define EXCP_NONE -1 /* sentinel value */ > -#define RISCV_EXCP_INST_ADDR_MIS 0x0 > -#define RISCV_EXCP_INST_ACCESS_FAULT 0x1 > -#define RISCV_EXCP_ILLEGAL_INST 0x2 > -#define RISCV_EXCP_BREAKPOINT 0x3 > -#define RISCV_EXCP_LOAD_ADDR_MIS 0x4 > -#define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5 > -#define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6 > -#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7 > -#define RISCV_EXCP_U_ECALL 0x8 > -#define RISCV_EXCP_S_ECALL 0x9 > -#define RISCV_EXCP_VS_ECALL 0xa > -#define RISCV_EXCP_M_ECALL 0xb > -#define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0 */ > -#define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0 */ > -#define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */ > -#define RISCV_EXCP_SEMIHOST 0x10 > -#define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14 > -#define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15 > -#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT 0x16 > -#define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17 > +typedef enum RiscVException { nits: looking at other places in the RISC-V codes, I believe it's better to name it "RISCVException" > + RISCV_EXCP_NONE = -1, /* sentinel value */ > + RISCV_EXCP_INST_ADDR_MIS = 0x0, > + RISCV_EXCP_INST_ACCESS_FAULT = 0x1, > + RISCV_EXCP_ILLEGAL_INST = 0x2, > + RISCV_EXCP_BREAKPOINT = 0x3, > + RISCV_EXCP_LOAD_ADDR_MIS = 0x4, > + RISCV_EXCP_LOAD_ACCESS_FAULT = 0x5, > + RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6, > + RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 0x7, > + RISCV_EXCP_U_ECALL = 0x8, > + RISCV_EXCP_S_ECALL = 0x9, > + RISCV_EXCP_VS_ECALL = 0xa, > + RISCV_EXCP_M_ECALL = 0xb, > + RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */ > + RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */ > + RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */ > + RISCV_EXCP_SEMIHOST = 0x10, > + RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14, > + RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15, > + RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16, > + RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17, > +} RiscVException; > > #define RISCV_EXCP_INT_FLAG 0x80000000 > #define RISCV_EXCP_INT_MASK 0x7fffffff > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 2a990f6253..63584b4a20 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -357,7 +357,7 @@ static void riscv_cpu_reset(DeviceState *dev) > env->mcause = 0; > env->pc = env->resetvec; > #endif > - cs->exception_index = EXCP_NONE; > + cs->exception_index = RISCV_EXCP_NONE; > env->load_res = -1; > set_default_nan_mode(1, &env->fp_status); > } > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 83a6bcfad0..af702f65b1 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -72,7 +72,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) > if (irqs) { > return ctz64(irqs); /* since non-zero */ > } else { > - return EXCP_NONE; /* indicates no pending interrupt */ > + return RISCV_EXCP_NONE; /* indicates no pending interrupt */ > } > } > #endif > @@ -1017,5 +1017,5 @@ void riscv_cpu_do_interrupt(CPUState *cs) > */ > > #endif > - cs->exception_index = EXCP_NONE; /* mark handled to qemu */ > + cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ > } > -- Otherwise, Reviewed-by: Bin Meng