* [PATCH] hw/riscv: opentitan: Fixup the PLIC context addresses
@ 2021-10-25 4:06 Alistair Francis
2021-10-25 4:16 ` Bin Meng
0 siblings, 1 reply; 3+ messages in thread
From: Alistair Francis @ 2021-10-25 4:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair23, Alistair Francis
From: Alistair Francis <alistair.francis@wdc.com>
Fixup the PLIC context address to correctly support the threshold and
claim register.
Fixes: ef63100648 ("hw/riscv: opentitan: Update to the latest build")
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/opentitan.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 83e1511f28..c531450b9f 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -161,8 +161,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18);
- qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200004);
- qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 4);
+ qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000);
+ qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8);
qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
--
2.31.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] hw/riscv: opentitan: Fixup the PLIC context addresses
2021-10-25 4:06 [PATCH] hw/riscv: opentitan: Fixup the PLIC context addresses Alistair Francis
@ 2021-10-25 4:16 ` Bin Meng
2021-10-25 22:33 ` Alistair Francis
0 siblings, 1 reply; 3+ messages in thread
From: Bin Meng @ 2021-10-25 4:16 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers, Alistair Francis
On Mon, Oct 25, 2021 at 12:07 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Fixup the PLIC context address to correctly support the threshold and
> claim register.
>
> Fixes: ef63100648 ("hw/riscv: opentitan: Update to the latest build")
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/opentitan.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] hw/riscv: opentitan: Fixup the PLIC context addresses
2021-10-25 4:16 ` Bin Meng
@ 2021-10-25 22:33 ` Alistair Francis
0 siblings, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2021-10-25 22:33 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Alistair Francis, Palmer Dabbelt,
Alistair Francis, qemu-devel@nongnu.org Developers
On Mon, Oct 25, 2021 at 2:16 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Mon, Oct 25, 2021 at 12:07 PM Alistair Francis
> <alistair.francis@opensource.wdc.com> wrote:
> >
> > From: Alistair Francis <alistair.francis@wdc.com>
> >
> > Fixup the PLIC context address to correctly support the threshold and
> > claim register.
> >
> > Fixes: ef63100648 ("hw/riscv: opentitan: Update to the latest build")
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > hw/riscv/opentitan.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
^ permalink raw reply [flat|nested] 3+ messages in thread
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2021-10-25 4:06 [PATCH] hw/riscv: opentitan: Fixup the PLIC context addresses Alistair Francis
2021-10-25 4:16 ` Bin Meng
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