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Mon, 05 Dec 2022 00:21:57 -0800 (PST) MIME-Version: 1.0 References: <20221201140811.142123-1-bmeng@tinylab.org> <20221201140811.142123-15-bmeng@tinylab.org> <4d2fa372f88dda106d80bd26806bc32c2a92d784.camel@wdc.com> In-Reply-To: <4d2fa372f88dda106d80bd26806bc32c2a92d784.camel@wdc.com> From: Bin Meng Date: Mon, 5 Dec 2022 16:21:46 +0800 Message-ID: Subject: Re: [PATCH 15/15] hw/intc: sifive_plic: Fix the pending register range check To: Wilfred Mallawa Cc: "bmeng@tinylab.org" , Alistair Francis , "qemu-devel@nongnu.org" , "bin.meng@windriver.com" , "palmer@dabbelt.com" , "qemu-riscv@nongnu.org" Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::130; envelope-from=bmeng.cn@gmail.com; helo=mail-lf1-x130.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Dec 2, 2022 at 8:28 AM Wilfred Mallawa wrote: > > On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote: > > The pending register upper limit is currently set to > > plic->num_sources >> 3, which is wrong, e.g.: considering > > plic->num_sources is 7, the upper limit becomes 0 which fails > > the range check if reading the pending register at pending_base. > > > > Fixes: 1e24429e40df ("SiFive RISC-V PLIC Block") > > Signed-off-by: Bin Meng > > > > --- > > > > hw/intc/sifive_plic.c | 5 +++-- > > 1 file changed, 3 insertions(+), 2 deletions(-) > > > > diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c > > index 7a6a358c57..a3fc8222c7 100644 > > --- a/hw/intc/sifive_plic.c > > +++ b/hw/intc/sifive_plic.c > > @@ -143,7 +143,8 @@ static uint64_t sifive_plic_read(void *opaque, > > hwaddr addr, unsigned size) > > uint32_t irq = (addr - plic->priority_base) >> 2; > > > > return plic->source_priority[irq]; > > - } else if (addr_between(addr, plic->pending_base, plic- > > >num_sources >> 3)) { > > + } else if (addr_between(addr, plic->pending_base, > > + (plic->num_sources + 31) >> 3)) { > why does adding specifically 31 work here? > Each pending register is 32-bit for 32 interrupt sources. Adding 31 is to round up to next pending register offset. Regards, Bin