From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: "Palmer Dabbelt" <palmer@dabbelt.com>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"Alistair Francis" <alistair23@gmail.com>
Subject: Re: [PATCH v3 9/9] target/riscv: Use a smaller guess size for no-MMU PMP
Date: Thu, 21 May 2020 09:52:16 +0800 [thread overview]
Message-ID: <CAEUhbmVfdwKERmdRzmh30xFOW9Chfu9v8P1LM8nxgK+nLheiTw@mail.gmail.com> (raw)
In-Reply-To: <c8b00dc5d38574f05be4c8c15549deb431aeba02.1589923785.git.alistair.francis@wdc.com>
On Wed, May 20, 2020 at 5:40 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/pmp.c | 14 +++++++++-----
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index 0e6b640fbd..607a991260 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -233,12 +233,16 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
> return true;
> }
>
> - /*
> - * if size is unknown (0), assume that all bytes
> - * from addr to the end of the page will be accessed.
> - */
> if (size == 0) {
> - pmp_size = -(addr | TARGET_PAGE_MASK);
> + if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
My previous comments were not fully addressed. I think the logic should be:
if (riscv_feature(env, RISCV_FEATURE_MMU))
Otherwise it does not match your comment and the commit title.
> + /*
> + * If size is unknown (0), assume that all bytes
> + * from addr to the end of the page will be accessed.
> + */
> + pmp_size = -(addr | TARGET_PAGE_MASK);
> + } else {
> + pmp_size = sizeof(target_ulong);
> + }
> } else {
> pmp_size = size;
> }
Regards,
Bin
next prev parent reply other threads:[~2020-05-21 1:53 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-19 21:31 [PATCH v3 0/9] RISC-V Add the OpenTitan Machine Alistair Francis
2020-05-19 21:31 ` [PATCH v3 1/9] riscv/boot: Add a missing header include Alistair Francis
2020-05-20 6:01 ` Philippe Mathieu-Daudé
2020-05-20 16:09 ` Alistair Francis
2020-05-19 21:31 ` [PATCH v3 2/9] target/riscv: Don't overwrite the reset vector Alistair Francis
2020-05-21 1:45 ` Bin Meng
2020-05-19 21:31 ` [PATCH v3 3/9] target/riscv: Add the lowRISC Ibex CPU Alistair Francis
2020-05-22 7:50 ` LIU Zhiwei
2020-05-26 17:12 ` Alistair Francis
2020-05-27 1:58 ` LIU Zhiwei
2020-05-27 16:44 ` Alistair Francis
2020-05-19 21:31 ` [PATCH v3 4/9] riscv: Initial commit of OpenTitan machine Alistair Francis
2020-05-19 21:31 ` [PATCH v3 5/9] hw/char: Initial commit of Ibex UART Alistair Francis
2020-05-19 21:31 ` [PATCH v3 6/9] hw/intc: Initial commit of lowRISC Ibex PLIC Alistair Francis
2020-05-19 21:31 ` [PATCH v3 7/9] riscv/opentitan: Connect the PLIC device Alistair Francis
2020-05-20 6:03 ` Philippe Mathieu-Daudé
2020-05-19 21:31 ` [PATCH v3 8/9] riscv/opentitan: Connect the UART device Alistair Francis
2020-05-20 6:03 ` Philippe Mathieu-Daudé
2020-05-19 21:31 ` [PATCH v3 9/9] target/riscv: Use a smaller guess size for no-MMU PMP Alistair Francis
2020-05-21 1:52 ` Bin Meng [this message]
2020-05-27 0:51 ` Alistair Francis
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