From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@opensource.wdc.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
"Bin Meng" <bin.meng@windriver.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"Markus Armbruster" <armbru@redhat.com>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Alistair Francis" <alistair23@gmail.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: Re: [PATCH v2 7/9] hw/riscv: Use error_fatal for SoC realisation
Date: Mon, 20 Dec 2021 15:38:13 +0800 [thread overview]
Message-ID: <CAEUhbmVrK3W4zRKnhkpq2e3vdSiNu2qaJe5y6nA+X_8ex3KLmg@mail.gmail.com> (raw)
In-Reply-To: <20211216045427.757779-8-alistair.francis@opensource.wdc.com>
On Thu, Dec 16, 2021 at 12:55 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> When realising the SoC use error_fatal instead of error_abort as the
> process can fail and report useful information to the user.
>
> Currently a user can see this:
>
> $ ../qemu/bld/qemu-system-riscv64 -M sifive_u -S -monitor stdio -display none -drive if=pflash
> QEMU 6.1.93 monitor - type 'help' for more information
> (qemu) Unexpected error in sifive_u_otp_realize() at ../hw/misc/sifive_u_otp.c:229:
> qemu-system-riscv64: OTP drive size < 16K
> Aborted (core dumped)
>
> Which this patch addresses
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reported-by: Markus Armbruster <armbru@redhat.com>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Reviewed-by: Markus Armbruster <armbru@redhat.com>
> ---
> hw/riscv/microchip_pfsoc.c | 2 +-
> hw/riscv/opentitan.c | 2 +-
> hw/riscv/sifive_e.c | 2 +-
> hw/riscv/sifive_u.c | 2 +-
> 4 files changed, 4 insertions(+), 4 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
next prev parent reply other threads:[~2021-12-20 17:50 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-16 4:54 [PATCH v2 0/9] A collection of RISC-V cleanups and improvements Alistair Francis
2021-12-16 4:54 ` [PATCH v2 1/9] hw/intc: sifive_plic: Add a reset function Alistair Francis
2021-12-16 8:16 ` Philippe Mathieu-Daudé
2021-12-21 8:00 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 2/9] hw/intc: sifive_plic: Cleanup the write function Alistair Francis
2021-12-16 4:54 ` [PATCH v2 3/9] hw/intc: sifive_plic: Cleanup the read function Alistair Francis
2021-12-16 4:54 ` [PATCH v2 4/9] hw/intc: sifive_plic: Cleanup remaining functions Alistair Francis
2021-12-21 8:22 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 5/9] target/riscv: Mark the Hypervisor extension as non experimental Alistair Francis
2021-12-16 5:59 ` Anup Patel
2021-12-20 2:52 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 6/9] target/riscv: Enable the Hypervisor extension by default Alistair Francis
2021-12-16 5:52 ` Anup Patel
2021-12-20 2:53 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 7/9] hw/riscv: Use error_fatal for SoC realisation Alistair Francis
2021-12-20 7:38 ` Bin Meng [this message]
2021-12-16 4:54 ` [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores Alistair Francis
2021-12-16 5:58 ` Anup Patel
2021-12-16 8:18 ` Philippe Mathieu-Daudé
2021-12-20 5:41 ` Alistair Francis
2021-12-20 7:39 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 9/9] hw/riscv: virt: Set the clock-frequency Alistair Francis
2021-12-16 5:52 ` Anup Patel
2021-12-20 7:51 ` Bin Meng
2021-12-21 6:32 ` Alistair Francis
2021-12-21 6:56 ` Bin Meng
2022-02-22 15:41 ` Peter Maydell
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