From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <alistair23@gmail.com>
Subject: Re: [PATCH v2 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC
Date: Thu, 5 Mar 2020 17:26:00 +0800 [thread overview]
Message-ID: <CAEUhbmW3VBUTTwAyh5EtAAZf-Mr4UFZtdNAaUBCyYfAZFUi1yg@mail.gmail.com> (raw)
In-Reply-To: <d1942aa2b5ce772070507bbe7c1cd1d280b36323.1583362888.git.alistair.francis@wdc.com>
On Thu, Mar 5, 2020 at 7:11 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> At present the board serial number is hard-coded to 1, and passed
> to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> the serial number to generate a unique MAC address for the on-chip
> ethernet controller. When multiple QEMU 'sifive_u' instances are
> created and connected to the same subnet, they all have the same
> MAC address hence it creates a unusable network.
>
> A new "serial" property is introduced to the sifive_u SoC to specify
> the board serial number. When not given, the default serial number
> 1 is used.
>
> Suggested-by: Bin Meng <bmeng.cn@gmail.com>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/sifive_u.c | 8 +++++++-
> include/hw/riscv/sifive_u.h | 2 ++
> 2 files changed, 9 insertions(+), 1 deletion(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
next prev parent reply other threads:[~2020-03-05 9:27 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-04 23:02 [PATCH v2 0/3] hw/riscv: Add a serial property to the sifive_u machine Alistair Francis
2020-03-04 23:02 ` [PATCH v2 1/3] riscv/sifive_u: Fix up file ordering Alistair Francis
2020-03-04 23:02 ` [PATCH v2 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC Alistair Francis
2020-03-05 9:26 ` Bin Meng [this message]
2020-03-04 23:02 ` [PATCH v2 3/3] riscv/sifive_u: Add a serial property to the sifive_u machine Alistair Francis
2020-03-04 23:52 ` [PATCH v2 0/3] hw/riscv: " no-reply
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