From: Bin Meng <bmeng.cn@gmail.com>
To: Anup Patel <anup.patel@wdc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Anup Patel <anup@brainfault.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v4 2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
Date: Wed, 8 Sep 2021 14:14:52 +0800 [thread overview]
Message-ID: <CAEUhbmWR-c-nwoDRYbvb__tHpVKDj2gQW5XVUAwEaDWbraYhJw@mail.gmail.com> (raw)
In-Reply-To: <20210831110603.338681-3-anup.patel@wdc.com>
On Tue, Aug 31, 2021 at 7:07 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> The RISC-V ACLINT is more modular and backward compatible with
> original SiFive CLINT so instead of duplicating the original
> SiFive CLINT implementation we upgrade the current SiFive CLINT
> implementation to RISC-V ACLINT implementation.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/intc/riscv_aclint.c | 373 +++++++++++++++++++++++----------
> hw/riscv/microchip_pfsoc.c | 9 +-
> hw/riscv/shakti_c.c | 11 +-
> hw/riscv/sifive_e.c | 11 +-
> hw/riscv/sifive_u.c | 9 +-
> hw/riscv/spike.c | 14 +-
> hw/riscv/virt.c | 14 +-
> include/hw/intc/riscv_aclint.h | 54 +++--
> 8 files changed, 339 insertions(+), 156 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
next prev parent reply other threads:[~2021-09-08 6:16 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-31 11:05 [PATCH v4 0/4] QEMU RISC-V ACLINT Support Anup Patel
2021-08-31 11:06 ` [PATCH v4 1/4] hw/intc: Rename sifive_clint sources to riscv_aclint sources Anup Patel
2021-08-31 11:06 ` [PATCH v4 2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT Anup Patel
2021-09-08 6:14 ` Bin Meng [this message]
2021-08-31 11:06 ` [PATCH v4 3/4] hw/riscv: virt: Re-factor FDT generation Anup Patel
2021-08-31 11:06 ` [PATCH v4 4/4] hw/riscv: virt: Add optional ACLINT support to virt machine Anup Patel
2021-09-29 4:07 ` [PATCH v4 0/4] QEMU RISC-V ACLINT Support Anup Patel
2021-09-29 4:22 ` Alistair Francis
2021-09-29 4:25 ` Anup Patel
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