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Thu, 22 Dec 2022 02:25:08 -0800 (PST) MIME-Version: 1.0 References: <20221221182300.307900-1-dbarboza@ventanamicro.com> <20221221182300.307900-2-dbarboza@ventanamicro.com> In-Reply-To: <20221221182300.307900-2-dbarboza@ventanamicro.com> From: Bin Meng Date: Thu, 22 Dec 2022 18:24:58 +0800 Message-ID: Subject: Re: [PATCH 01/15] tests/avocado: add RISC-V opensbi boot test To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Bin Meng , Cleber Rosa , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Wainer dos Santos Moschetta , Beraldo Leal Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Dec 22, 2022 at 2:29 AM Daniel Henrique Barboza wrote: > > This test is used to do a quick sanity check to ensure that we're able > to run the existing QEMU FW image. > > 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and > 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | > RISCV32_BIOS_BIN firmware with minimal options. > > Cc: Cleber Rosa > Cc: Philippe Mathieu-Daud=C3=A9 > Cc: Wainer dos Santos Moschetta > Cc: Beraldo Leal > Signed-off-by: Daniel Henrique Barboza > --- > tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ > 1 file changed, 65 insertions(+) > create mode 100644 tests/avocado/riscv_opensbi.py > > diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi= .py > new file mode 100644 > index 0000000000..abc99ced30 > --- /dev/null > +++ b/tests/avocado/riscv_opensbi.py > @@ -0,0 +1,65 @@ > +# opensbi boot test for RISC-V machines > +# > +# Copyright (c) 2022, Ventana Micro > +# > +# This work is licensed under the terms of the GNU GPL, version 2 or > +# later. See the COPYING file in the top-level directory. > + > +from avocado_qemu import QemuSystemTest > +from avocado_qemu import wait_for_console_pattern > + > +class RiscvOpensbi(QemuSystemTest): > + """ > + :avocado: tags=3Daccel:tcg > + """ > + timeout =3D 5 > + > + def test_riscv64_virt(self): > + """ > + :avocado: tags=3Darch:riscv64 > + :avocado: tags=3Dmachine:virt > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > + > + def test_riscv64_spike(self): > + """ > + :avocado: tags=3Darch:riscv64 > + :avocado: tags=3Dmachine:spike > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > + > + def test_riscv64_sifive_u(self): > + """ > + :avocado: tags=3Darch:riscv64 > + :avocado: tags=3Dmachine:sifive_u > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > + > + def test_riscv32_virt(self): > + """ > + :avocado: tags=3Darch:riscv32 > + :avocado: tags=3Dmachine:virt > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') How about testing riscv32_spike too? > + > + def test_riscv32_sifive_u(self): > + """ > + :avocado: tags=3Darch:riscv32 > + :avocado: tags=3Dmachine:sifive_u > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > -- Regards, Bin