From: Bin Meng <bmeng.cn@gmail.com>
To: Jonathan Behrens <jonathan@fintelia.io>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
"Sagar Karandikar" <sagark@eecs.berkeley.edu>,
"Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>,
"Palmer Dabbelt" <palmer@sifive.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>
Subject: Re: [PATCH v4 2/3] target/riscv: Expose "priv" register for GDB for reads
Date: Tue, 15 Oct 2019 16:38:27 +0800 [thread overview]
Message-ID: <CAEUhbmXn-j42AK_wq1WJ-hWMt9XgBFGRNayGa80M2=jVC1F+-g@mail.gmail.com> (raw)
In-Reply-To: <20191014154529.287048-3-jonathan@fintelia.io>
On Mon, Oct 14, 2019 at 11:53 PM Jonathan Behrens <jonathan@fintelia.io> wrote:
>
> This patch enables a debugger to read the current privilege level via a virtual
> "priv" register. When compiled with CONFIG_USER_ONLY the register is still
> visible but always reports the value zero.
>
> Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
> ---
> configure | 4 ++--
> gdb-xml/riscv-32bit-virtual.xml | 11 +++++++++++
> gdb-xml/riscv-64bit-virtual.xml | 11 +++++++++++
> target/riscv/gdbstub.c | 23 +++++++++++++++++++++++
> 4 files changed, 47 insertions(+), 2 deletions(-)
> create mode 100644 gdb-xml/riscv-32bit-virtual.xml
> create mode 100644 gdb-xml/riscv-64bit-virtual.xml
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
next prev parent reply other threads:[~2019-10-15 8:40 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-14 15:45 [PATCH v4 0/3] target/riscv: Expose "priv" register for GDB Jonathan Behrens
2019-10-14 15:45 ` [PATCH v4 1/3] target/riscv: Tell gdbstub the correct number of CSRs Jonathan Behrens
2019-10-14 15:45 ` [PATCH v4 2/3] target/riscv: Expose "priv" register for GDB for reads Jonathan Behrens
2019-10-14 18:00 ` Alistair Francis
2019-10-15 8:38 ` Bin Meng [this message]
2019-10-14 15:45 ` [PATCH v4 3/3] target/riscv: Make the priv register writable by GDB Jonathan Behrens
2019-10-18 18:35 ` [PATCH v4 0/3] target/riscv: Expose "priv" register for GDB Palmer Dabbelt
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