From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 42550EDE989 for ; Fri, 15 Sep 2023 02:54:10 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qgyxu-00038A-T6; Thu, 14 Sep 2023 22:53:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qgyxs-000359-NR; Thu, 14 Sep 2023 22:53:52 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qgyxp-000328-GP; Thu, 14 Sep 2023 22:53:51 -0400 Received: by mail-pg1-x534.google.com with SMTP id 41be03b00d2f7-573ccec985dso1323996a12.2; Thu, 14 Sep 2023 19:53:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1694746427; x=1695351227; darn=nongnu.org; h=cc:to:subject:message-id:date:from:mime-version:from:to:cc:subject :date:message-id:reply-to; bh=8jXCHtEJAWZeoPIuYXVU75s++ZwBDA0cQTXgVqcpMPo=; b=b3N2Lo7Py9KYv3RltcLR129sD/ie0ZCmf8S2TyipsjUD+fK6iv05wO2tzJn30WV3lF +0ry7bJwffuKQLkoy4DQn6WHueGy0ID4rnBnQlE6EKZaO6jgc1R2Vyy4phuOtr3E8upH PUGZskXrtsbpTEQeneu3KHO4FmEc/qO+hZ6zhgW9+1q1/SqEPMpH6XJi+Xwz0Kw/yG+2 cZ70TdjYRIqI2BK/z3Fld5pYAUZhML3e6sV7JDzx4cIgBRNNuCz6K3ixhYNzdETPDZkH 3KMOpBL/+MbPs7d0c5xzO4hlHFg2Y8BrJVAj1zq6obQjz8igmW9sUCZPzZ+wqMk9DFiA m81g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694746427; x=1695351227; h=cc:to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=8jXCHtEJAWZeoPIuYXVU75s++ZwBDA0cQTXgVqcpMPo=; b=Jo1lsF1vlqS4pvMXkS6Ebq2wxSYMdCAGG0FL49De0d2F51OV2eE8taVMnH93KlcE+y Cbo3hvnQVxPluoK6XhDvL+U5myveOyCZ4I8iBRdFGqswLxlOdBzh9KnMftTX7r5tk/HT ESKMLzRuN5dmKeRGpTF6ISyoKv8pEZhwfXo229vv7LCJPZdZN8vQAW7MC2/zoZhVPZq6 XC1FWhKA5NHZWjl20Cz47Z30/B66uTvARsrXbbTyMHDOkmq78zAeHrn+PEKtvbVUdWjl OxHhU9NZpIFyB/Y2MUfIP9qFMqN3lrZkZq7wgK7DqDsHehGOvSdHNdccE3ex0sR4xmGo uVXQ== X-Gm-Message-State: AOJu0YxL8gds4qpjQN6/bjcvbpQ2m/9KpwRQNvfrsN6VP5KROWAwo3Ix 2z4HBUMPWtRafstEksmDEKpyQQv20Ja+3fJP10U= X-Google-Smtp-Source: AGHT+IHFMWPyxlMtBJ55J1VOEuExrJpqmlkLNv0qZmYG3DdiB6/wWL2+3PQaD5QCAiiFz5gWKkTDEsMvF/orqPZQPJw= X-Received: by 2002:a17:90a:fd98:b0:274:686d:497b with SMTP id cx24-20020a17090afd9800b00274686d497bmr301145pjb.27.1694746427322; Thu, 14 Sep 2023 19:53:47 -0700 (PDT) MIME-Version: 1.0 From: =?UTF-8?B?5by15ZOy5ZiJ?= Date: Fri, 15 Sep 2023 10:53:36 +0800 Message-ID: Subject: Re: [PATCH v2] target/riscv: update checks on writing pmpcfg for Smepmp version 1.0 To: Andrew Jones Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, alistair.francis@wdc.com, Mayuresh Chitale , Che-Chia Chang Content-Type: multipart/alternative; boundary="000000000000c8f9e706055ce62d" Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=vivahavey@gmail.com; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_KAM_HTML_FONT_INVALID=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --000000000000c8f9e706055ce62d Content-Type: text/plain; charset="UTF-8" > On Fri, Sep 08, 2023 at 04:38:34PM +0800, Alvin Chang wrote: > > Current checks on writing pmpcfg for Smepmp follows Smepmp version > > 0.9.1. However, Smepmp specification has already been ratified, and > > there are some differences between version 0.9.1 and 1.0. In this > > commit we update the checks of writing pmpcfg to follow Smepmp version > 1.0. > > > > When mseccfg.MML is set, the constraints to modify PMP rules are: > > 1. Locked rules connot be removed or modified until a PMP reset, unless > > mseccfg.RLB is set. > > 2. From Smepmp specification version 1.0, chapter 2 section 4b: > > Adding a rule with executable privileges that either is M-mode-only > > or a locked Shared-Region is not possible and such pmpcfg writes are > > ignored, leaving pmpcfg unchanged. > > > > The commit transfers the value of pmpcfg into the index of the Smepmp > > truth table, and checks the rules by aforementioned specification > > changes. > > > > Signed-off-by: Alvin Chang > > --- > > Changes from v1: Convert ePMP over to Smepmp. > > > > target/riscv/pmp.c | 51 > > ++++++++++++++++++++++++++++++++++++++-------- > > 1 file changed, 42 insertions(+), 9 deletions(-) > > > > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index > > 9d8db493e6..d1c3fc1e4f 100644 > > --- a/target/riscv/pmp.c > > +++ b/target/riscv/pmp.c > > @@ -98,16 +98,49 @@ static bool pmp_write_cfg(CPURISCVState *env, > uint32_t pmp_index, uint8_t val) > > locked = false; > > } > > > > - /* mseccfg.MML is set */ > > - if (MSECCFG_MML_ISSET(env)) { > > - /* not adding execute bit */ > > - if ((val & PMP_LOCK) != 0 && (val & PMP_EXEC) != > PMP_EXEC) { > > - locked = false; > > - } > > - /* shared region and not adding X bit */ > > - if ((val & PMP_LOCK) != PMP_LOCK && > > - (val & 0x7) != (PMP_WRITE | PMP_EXEC)) { > > + /* > > + * mseccfg.MML is set. Locked rules cannot be removed or > modified > > + * until a PMP reset. Besides, from Smepmp specification > version 1.0 > > + * , chapter 2 section 4b says: > > + * Adding a rule with executable privileges that either is > > + * M-mode-only or a locked Shared-Region is not possible > and such > > + * pmpcfg writes are ignored, leaving pmpcfg unchanged. > > + */ > > + if (MSECCFG_MML_ISSET(env) && !pmp_is_locked(env, > pmp_index)) { > > + /* > > + * Convert the PMP permissions to match the truth > table in the > > + * ePMP spec. > > + */ > > + const uint8_t epmp_operation = > > + ((val & PMP_LOCK) >> 4) | ((val & PMP_READ) << > 2) | > > + (val & PMP_WRITE) | ((val & PMP_EXEC) >> 2); > > + > > + switch (epmp_operation) { > > + /* pmpcfg.L = 0. Neither M-mode-only nor locked > Shared-Region */ > > + case 0: > > + case 1: > > + case 2: > > + case 3: > > + case 4: > > + case 5: > > + case 6: > > + case 7: > > + /* pmpcfg.L = 1 and pmpcfg.X = 0 (but case 10 is not > allowed) */ > > + case 8: > > case 0 ... 8: > OK, will apply case ranges. > > + case 12: > > + case 14: > > + /* pmpcfg.LRWX = 1111 */ > > + case 15: /* Read-only locked Shared-Region on all > > + modes */ > > locked = false; > > + break; > > + /* Other rules which add new code regions are not > allowed */ > > + case 9: > > + case 10: /* Execute-only locked Shared-Region on all > modes */ > > + case 11: > > case 9 ... 11: > > And why not put these cases in numerical order? > Agree, I will put them in numerical order. > > + case 13: > > + break; > > + default: > > + g_assert_not_reached(); > > } > > } > > } else { > > -- > > 2.34.1 > > > > > > It looks like this patch has overlap with > > https://lore.kernel.org/all/20230907062440.1174224-1-mchitale@ventanamicr > o.com/ > > Maybe you and Mayuresh can work together on a final patch. > It seems Mayuresh's patch is to reset PMP entries and mseccfg when CPU resets. This patch is to check the valid setting of pmpcfg at runtime, when CPU supports Smepmp. I think they are two independent patches. > Thanks, > drew --000000000000c8f9e706055ce62d Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

> On Fri, = Sep 08, 2023 at 04:38:34PM +0800, Alvin Chang wrote:

> > Current checks on wr= iting pmpcfg for Smepmp follows Smepmp version

> > 0.9.1. However, Smep= mp specification has already been ratified, and

> > there are some diffe= rences between version 0.9.1 and 1.0. In this

> > commit we update the= checks of writing pmpcfg to follow Smepmp version

> 1.0.

> >

> > When mseccfg.MML is = set, the constraints to modify PMP rules are:

> > 1. Locked rules conn= ot be removed or modified until a PMP reset, unless

> >=C2=A0=C2=A0=C2=A0 ms= eccfg.RLB is set.

> > 2. From Smepmp speci= fication version 1.0, chapter 2 section 4b:

> >=C2=A0=C2=A0=C2=A0 Ad= ding a rule with executable privileges that either is M-mode-only

> >=C2=A0=C2=A0=C2=A0 or= a locked Shared-Region is not possible and such pmpcfg writes are

> >=C2=A0=C2=A0=C2=A0 ig= nored, leaving pmpcfg unchanged.

> >

> > The commit transfers= the value of pmpcfg into the index of the Smepmp

> > truth table, and che= cks the rules by aforementioned specification

> > changes.

> >

> > Signed-off-by: Alvin= Chang <alvinga@andestech.com>

> > ---

> > Changes from v1: Con= vert ePMP over to Smepmp.

> >

> >=C2=A0 target/riscv/p= mp.c | 51

> > ++++++++++++++++++++++++++++++++++++++--------

> >=C2=A0 1 file changed= , 42 insertions(+), 9 deletions(-)

> >

> > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index

> > 9d8db493e6..d1c3fc1e= 4f 100644

> > --- a/target/riscv/p= mp.c

> > +++ b/target/riscv/p= mp.c

> > @@ -98,16 +98,49 @@ = static bool pmp_write_cfg(CPURISCVState *env,

> uint32_t pmp_index, uint8= _t val)

> >=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 locked =3D false;

> >=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 }

> >

> > -=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* mseccfg.MML is set */

> > -=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (MSECCFG_MML_ISSET(env)= ) {

> > -=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /*= not adding execute bit */

> > -=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if= ((val & PMP_LOCK) !=3D 0 && (val & PMP_EXEC) !=3D

> PMP_EXEC) {

> > -=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 locked =3D false;

> > -=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 }<= /span>

> > -=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /*= shared region and not adding X bit */

> > -=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if= ((val & PMP_LOCK) !=3D PMP_LOCK &&

> > -=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 (val & 0x7) !=3D (PMP_WRITE | PMP_EXEC)) {

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /*

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * mseccfg.MML is set= . Locked rules cannot be removed or

> modified

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * until a PMP reset.= Besides, from Smepmp specification

> version 1.0

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * , chapter 2 sectio= n 4b says:

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * Adding a rule with= executable privileges that either is

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * M-mode-only or a l= ocked Shared-Region is not possible

> and such

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * pmpcfg writes are = ignored, leaving pmpcfg unchanged.

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 */

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (MSECCFG_MML_ISSET(env) && !pmp_is_locked(env,

> pmp_index)) {

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /*=

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 * Convert the PMP permissions to match the truth

> table in the

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 * ePMP spec.

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 */

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 co= nst uint8_t epmp_operation =3D

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 ((val & PMP_LOCK) >> 4) | ((val & PMP_READ) <<

> 2) |

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 (val & PMP_WRITE) | ((val & PMP_EXEC) >> 2);

> > +

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sw= itch (epmp_operation) {

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /*= pmpcfg.L =3D 0. Neither M-mode-only nor locked

> Shared-Region */

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ca= se 0:

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ca= se 1:

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ca= se 2:

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ca= se 3:

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ca= se 4:

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ca= se 5:

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ca= se 6:

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ca= se 7:

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /*= pmpcfg.L =3D 1 and pmpcfg.X =3D 0 (but case 10 is not

> allowed) */

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ca= se 8:

>

> case 0 ... 8:

>


OK, will apply case ranges.


> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ca= se 12:

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ca= se 14:

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /*= pmpcfg.LRWX =3D 1111 */

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ca= se 15:=C2=A0 /* Read-only locked Shared-Region on all

> > + modes */

> >=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 locked =3D false;

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 break;

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /*= Other rules which add new code regions are not

> allowed */

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ca= se 9:

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ca= se 10:=C2=A0 /* Execute-only locked Shared-Region on all

> modes */

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ca= se 11:

>

> case 9 ... 11:

>

> And why not put these cas= es in numerical order?

>


Agree, I will put them in numerical order.


> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ca= se 13:

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 break;

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 de= fault:

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 g_assert_not_reached();

> >=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 }

> >=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 }

> >=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } else {

> > --

> > 2.34.1

> >

> >

>

> It looks like this patch = has overlap with

>

> https://lore.kernel.org/= all/20230907062440.1174224-1-mchitale@ventanamicr

> o.com/

>

> Maybe you and Mayuresh ca= n work together on a final patch.

>


It seems Mayuresh's patch is to reset PMP entries and m= seccfg when CPU resets.

This patch is to = check the valid setting of pmpcfg at runtime, when CPU supports Smepmp.

=

I think they are two independent patches.


> Thanks,

> drew

--000000000000c8f9e706055ce62d--