From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2D447C4167B for ; Wed, 6 Dec 2023 05:38:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rAkap-000517-Pp; Wed, 06 Dec 2023 00:37:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rAkag-00050O-U0; Wed, 06 Dec 2023 00:36:59 -0500 Received: from mail-ot1-x335.google.com ([2607:f8b0:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rAkae-0005IO-Jv; Wed, 06 Dec 2023 00:36:58 -0500 Received: by mail-ot1-x335.google.com with SMTP id 46e09a7af769-6d857f6f1c0so3837315a34.0; Tue, 05 Dec 2023 21:36:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1701841014; x=1702445814; darn=nongnu.org; h=cc:to:subject:message-id:date:from:mime-version:from:to:cc:subject :date:message-id:reply-to; bh=tkEC1fbfGrG2MzC4baBJMznHZnsR7/zxc277fQG6j4w=; b=Cl2WCJOB36wx4jPT1MsRgmcQ7cBX4VbsSVbUl8Key2/AIQy5Nvzlnl+CfpkuCLTdpG ANId7Uj/QEI2Y9NFUPgDW8oIpnu5hdc2ZJ4eIA5bjSFAo/fx5yB8tsrxXdQpfSoXhfx2 yWV814kYjggemyxzaK0Pam3WiXpCcy4XpokkOfKGyf9ciZWGYuzDZrbc1+NaQVC5buwb 4yFPLMsx1J0S1ebmCnDSEE22CeD/cXaaq1ZvxHkF5DcA26WJK6UOWez9UewvG7DL7xTB u2OPQPw6Zb8iQn+nKO3RWD0h/R48pvjZ3DkEoJLCUwU/RyUYFyY9LPEN5yK2JfHe3qF8 jyYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701841014; x=1702445814; h=cc:to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=tkEC1fbfGrG2MzC4baBJMznHZnsR7/zxc277fQG6j4w=; b=hFXfq1ll/8jqN8Mzxd2T3VHVVFfGf+7ZMk0R4iu5bpc//wEu/0V53rpOviiEw5+9Tn 04anHSA6UVDOx337ZW1vv6U72hX6PamRtCmcnGrX9Bp3on3gd7RhHGxfy029HvB1yY0z JOJ0q8DteJqfz/itWe+HwW55qUxWihC3eqoeacgC1ph+A88qB8vjjJaq7+IB0T1dQM7K 8zQBcaIDrRxpj9eksAG1oMs/BtOAF/AxfpMH2qnUTWf4gogDfwwzMXJ8L6l4ZZDjcTaA iyUIubWbvdoKvNNLp5nnBI8LuztJKayNSazYa0+HV5faNRHQsUs4BRTM0d/+T1ePfHnb DZDw== X-Gm-Message-State: AOJu0Yyh3CcHy11EANsGR/qbrNKtpgw+OeAaaz+DVKsGY02s14JkzVx4 tHfarYJ2ju0mRJuQ7mNXpsHb2Amb4aMWZptPXzkdo4CRj4FtfA== X-Google-Smtp-Source: AGHT+IEQQE0Udu4/1R0gebnYJ0cabrVmsPiZDc41fZCPWj3YVbQG35pE3IVqApgmyJ9AG5Y6MsSp15Jd1rdfDcR28YY= X-Received: by 2002:a05:6830:1416:b0:6d8:1bf7:df35 with SMTP id v22-20020a056830141600b006d81bf7df35mr517824otp.29.1701841014313; Tue, 05 Dec 2023 21:36:54 -0800 (PST) MIME-Version: 1.0 From: Alvin Chang Date: Wed, 6 Dec 2023 13:36:38 +0800 Message-ID: Subject: Re: [PATCH v5] target/riscv: update checks on writing pmpcfg for Smepmp to version 1.0 To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, alistair.francis@wdc.com Cc: liweiwei@iscas.ac.cn Content-Type: multipart/alternative; boundary="0000000000001f5868060bd0bd2f" Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=vivahavey@gmail.com; helo=mail-ot1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_KAM_HTML_FONT_INVALID=0.01, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --0000000000001f5868060bd0bd2f Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: Alistair Francis > Sent: Wednesday, December 6, 2023 11:39 AM > To: Alvin Che-Chia Chang(=E5=BC=B5=E5=93=B2=E5=98=89) > Cc: qemu-riscv@nongnu.org; qemu-devel@nongnu.org; > alistair.francis@wdc.com; liweiwei@iscas.ac.cn > Subject: Re: [PATCH v5] target/riscv: update checks on writing pmpcfg for > Smepmp to version 1.0 > > On Tue, Nov 14, 2023 at 12:24=E2=80=AFPM Alvin Chang via > wrote: > > > > Current checks on writing pmpcfg for Smepmp follows Smepmp version > > 0.9.1. However, Smepmp specification has already been ratified, and > > there are some differences between version 0.9.1 and 1.0. In this > > commit we update the checks of writing pmpcfg to follow Smepmp version > > 1.0. > > > > When mseccfg.MML is set, the constraints to modify PMP rules are: > > 1. Locked rules cannot be removed or modified until a PMP reset, unless > > mseccfg.RLB is set. > > 2. From Smepmp specification version 1.0, chapter 2 section 4b: > > Adding a rule with executable privileges that either is M-mode-only > > or a locked Shared-Region is not possible and such pmpcfg writes are > > ignored, leaving pmpcfg unchanged. > > > > The commit transfers the value of pmpcfg into the index of the Smepmp > > truth table, and checks the rules by aforementioned specification > > changes. > > > > Signed-off-by: Alvin Chang > > --- > > Changes from v4: Rebase on master. > > > > Changes from v3: Modify "epmp_operation" to "smepmp_operation". > > > > Changes from v2: Adopt switch case ranges and numerical order. > > > > Changes from v1: Convert ePMP over to Smepmp. > > > > target/riscv/pmp.c | 40 ++++++++++++++++++++++++++++++++-------- > > 1 file changed, 32 insertions(+), 8 deletions(-) > > > > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index > > 162e88a90a..4069514069 100644 > > --- a/target/riscv/pmp.c > > +++ b/target/riscv/pmp.c > > @@ -102,16 +102,40 @@ static bool pmp_write_cfg(CPURISCVState *env, > uint32_t pmp_index, uint8_t val) > > locked =3D false; > > } > > > > - /* mseccfg.MML is set */ > > - if (MSECCFG_MML_ISSET(env)) { > > - /* not adding execute bit */ > > - if ((val & PMP_LOCK) !=3D 0 && (val & PMP_EXEC) !=3D > PMP_EXEC) { > > + /* > > + * mseccfg.MML is set. Locked rules cannot be removed or > modified > > + * until a PMP reset. Besides, from Smepmp specification > version 1.0 > > + * , chapter 2 section 4b says: > > + * Adding a rule with executable privileges that either is > > + * M-mode-only or a locked Shared-Region is not possible > and such > > + * pmpcfg writes are ignored, leaving pmpcfg unchanged. > > + */ > > + if (MSECCFG_MML_ISSET(env) && !pmp_is_locked(env, > > + pmp_index)) { > > This is tricky and took me a while to get my head around. > > From what I can tell, there is a bug in the spec. > > The spec specifically states that: > > """ > The meaning of pmpcfg.L changes: Instead of marking a rule as locked and > enforced in all modes, it now marks a rule as M-mode-only when set and > S/U-mode-only when unset. > """ > > So the check for !pmp_is_locked() sounds correct. > > But then they add: > > """ > The formerly reserved encoding of pmpcfg.RW=3D01, and the encoding > pmpcfg.LRWX=3D1111, now encode a Shared-Region. > """ > > Which contradicts what they just said. Yes you are right, it seems there are some misleading words. > > I *think* we want to ignore the locked bit here. We don't actually care if it's > already set, instead we care if the region is an M-mode only region from the > 2.1 table The check for !pmp_is_locked() is because spec says (below table 2.1): "*Locked rules cannot be removed or modified until a PMP reset, unless mseccfg.RLB is set." It is not related to M-mode-only or S/U-mode-only or Shared-Region. In other words, a pmpcfg where the pmpcfg.L bit was set can not be configured anymore. Therefore, I think we should not ignore it here, since we are trying to write a new value into the pmpcfg. If we ignore it, the locked pmpcfg will be modified and it would violate the spec. If the pmpcfg was not locked, we also need to check the new value that the user wants to write. Because chapter 2 section 4b says: "Adding a rule with executable privileges that either is M-mode-only or a locked Shared-Region is not possible and such pmpcfg writes are ignored, leaving pmpcfg unchanged". This checking is implemented as that switch-case statement, based on table 2.1 truth table. Alvin Chang > > I think the best bet here is to create a helper function that takes a pmpcfg > value and returns if it is M-mode only. Then we should check if the current > pmp_index is M-mode only OR if we are adding one and then reject that. > > Does that make sense? > > Alistair > > > + /* > > + * Convert the PMP permissions to match the truth > table in the > > + * Smepmp spec. > > + */ > > + const uint8_t smepmp_operation =3D > > + ((val & PMP_LOCK) >> 4) | ((val & PMP_READ) << > 2) | > > + (val & PMP_WRITE) | ((val & PMP_EXEC) >> 2); > > + > > + switch (smepmp_operation) { > > + case 0 ... 8: > > locked =3D false; > > - } > > - /* shared region and not adding X bit */ > > - if ((val & PMP_LOCK) !=3D PMP_LOCK && > > - (val & 0x7) !=3D (PMP_WRITE | PMP_EXEC)) { > > + break; > > + case 9 ... 11: > > + break; > > + case 12: > > + locked =3D false; > > + break; > > + case 13: > > + break; > > + case 14: > > + case 15: > > locked =3D false; > > + break; > > + default: > > + g_assert_not_reached(); > > } > > } > > } else { > > -- > > 2.34.1 > > > > --0000000000001f5868060bd0bd2f Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

> -----Original Message-----

> From: Alistair Francis &l= t;alistair23@gmail.com>

> Sent: Wednesday, December= 6, 2023 11:39 AM

> To: Alvin Che-Chia Chang(= =E5=BC=B5=E5=93=B2=E5=98=89) <alvinga@andestech.com><= /span>

> Cc: qemu-riscv@nongnu.org; qemu-devel@nongnu.org;

> alistair.francis@wdc.com; liweiwei@iscas.ac.cn

> Subject: Re: [PATCH v5] t= arget/riscv: update checks on writing pmpcfg for

> Smepmp to version 1.0

>

> On Tue, Nov 14, 2023 at 1= 2:24=E2=80=AFPM Alvin Chang via <qemu-devel@nongnu.org>

> wrote:

> >

> > Current checks on wr= iting pmpcfg for Smepmp follows Smepmp version

> > 0.9.1. However, Smep= mp specification has already been ratified, and

> > there are some diffe= rences between version 0.9.1 and 1.0. In this

> > commit we update the= checks of writing pmpcfg to follow Smepmp version

> > 1.0.

> >

> > When mseccfg.MML is = set, the constraints to modify PMP rules are:

> > 1. Locked rules cann= ot be removed or modified until a PMP reset, unless

> >=C2=A0=C2=A0=C2=A0 ms= eccfg.RLB is set.

> > 2. From Smepmp speci= fication version 1.0, chapter 2 section 4b:

> >=C2=A0=C2=A0=C2=A0 Ad= ding a rule with executable privileges that either is M-mode-only

> >=C2=A0=C2=A0=C2=A0 or= a locked Shared-Region is not possible and such pmpcfg writes are

> >=C2=A0=C2=A0=C2=A0 ig= nored, leaving pmpcfg unchanged.

> >

> > The commit transfers= the value of pmpcfg into the index of the Smepmp

> > truth table, and che= cks the rules by aforementioned specification

> > changes.

> >

> > Signed-off-by: Alvin= Chang <alvinga@andestech= .com>

> > ---

> > Changes from v4: Reb= ase on master.

> >

> > Changes from v3: Mod= ify "epmp_operation" to "smepmp_operation".

> >

> > Changes from v2: Ado= pt switch case ranges and numerical order.

> >

> > Changes from v1: Con= vert ePMP over to Smepmp.

> >

> >=C2=A0 target/riscv/p= mp.c | 40 ++++++++++++++++++++++++++++++++--------

> >=C2=A0 1 file changed= , 32 insertions(+), 8 deletions(-)

> >

> > diff --git a/target/= riscv/pmp.c b/target/riscv/pmp.c index

> > 162e88a90a..40695140= 69 100644

> > --- a/target/riscv/p= mp.c

> > +++ b/target/riscv/p= mp.c

> > @@ -102,16 +102,40 @= @ static bool pmp_write_cfg(CPURISCVState *env,

> uint32_t pmp_index, uint8= _t val)

> >=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 locked =3D false;

> >=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 }

> >

> > -=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* mseccfg.MML is set */

> > -=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (MSECCFG_MML_ISSET(env)) {

> > -=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* not adding execute bit */

> > -=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if ((val & PMP_LOCK) !=3D 0 && (val & PMP_EXEC) !=3D

> PMP_EXEC) {

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /*

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * mseccfg.MML is set. Locked rules cannot be removed or

> modified

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * until a PMP reset. Besides, from Smepmp specification

> version 1.0

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * , chapter 2 section 4b says:

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * Adding a rule with executable privileges that either is

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * M-mode-only or a locked Shared-Region is not possible

> and such

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * pmpcfg writes are ignored, leaving pmpcfg unchanged.

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 */

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (MSECCFG_MML_ISSET(env) && !pmp_is_locked(env,

> > + pmp_index)) {

>

> This is tricky and took m= e a while to get my head around.

>

> From what I can tell, the= re is a bug in the spec.

>

> The spec specifically sta= tes that:

>

> """=

> The meaning of pmpcfg.L c= hanges: Instead of marking a rule as locked and

> enforced in all modes, it= now marks a rule as M-mode-only when set and

> S/U-mode-only when unset.=

> """=

>

> So the check for !pmp_is_= locked() sounds correct.

>

> But then they add:=

>

> """=

> The formerly reserved enc= oding of pmpcfg.RW=3D01, and the encoding

> pmpcfg.LRWX=3D1111, now e= ncode a Shared-Region.

> """=

>

> Which contradicts what th= ey just said.


Yes you are right, it= seems there are some misleading words.

<= span lang=3D"EN-US">

>

> I *think* we want to igno= re the locked bit here. We don't actually care if it's

> already set, instead we c= are if the region is an M-mode only region from the

> 2.1 table


The check for !pmp_is_lo= cked() is because spec says (below table 2.1):

"*Locked rules cannot be removed or modified until a PMP reset, unl= ess mseccfg.RLB is set."

It is not rel= ated to M-mode-only or S/U-mode-only or Shared-Region.


In ot= her words, a pmpcfg where the pmpcfg.L bit was set can not be configured an= ymore. Therefore, I think we should not ignore it here, since we are trying= to write a new value into the pmpcfg. If we ignore it, the locked pmpcfg w= ill be modified and it would=C2=A0violate the spec.


If the pmpcfg was not locked, we also = need to check the new value that the user wants to write. Because=C2=A0chapter 2 section 4b says: "<= span style=3D"font-size:12pt">Adding a rule with executable privileges that= either is M-mode-only=C2=A0or a lock= ed Shared-Region is not possible and such pmpcfg writes are=C2=A0ignored, leaving pmpcfg unchanged". This c= hecking is implemented as that switch-case statement,=C2=A0based on table 2= .1 truth table.


Alvin Chang

<= span lang=3D"EN-US">

>

> I think the best bet here= is to create a helper function that takes a pmpcfg

> value and returns if it i= s M-mode only. Then we should check if the current

> pmp_index is M-mode only = OR if we are adding one and then reject that.

>

> Does that make sense?

>

> Alistair

>

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /*=

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 * Convert the PMP permissions to match the truth

> table in the

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 * Smepmp spec.

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 */

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 const uint8_t smepmp_operation =3D

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 ((val & PMP_LOCK) >> 4) | ((val & PMP_READ) <<

> 2) |

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 (val & PMP_WRITE) | ((val & PMP_EXEC) >> 2);

> > +

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 switch (smepmp_operation) {

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case 0 ... 8:

> >=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 locked =3D false;

> > -=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 }<= /span>

> > -=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* shared region and not adding X bit */

> > -=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if ((val & PMP_LOCK) !=3D PMP_LOCK &&

> > -=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 (val & 0x7) !=3D (PMP_WRITE | PMP_EXEC)) {

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 break;

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case 9 ... 11:

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 break;

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case 12:

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 locked =3D false;

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 break;

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case 13:

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 break;

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case 14:

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case 15:

> >=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 locked =3D false;

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 break;

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 default:

> > +=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 g_assert_not_reached();

> >=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 }

> >=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 }

> >=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } else {

> > --

> > 2.34.1

> >

> >

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