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envelope-from=vacha.bhavsar@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --000000000000a50d0c063dd52710 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi, Regarding the definition of ZA as a 'vector of bytes' in the gdb documentation, the choice that we have made in representing it as a vector of vectors of bytes is based on the xml retrieved by the native gdb client when run on a host with SME capabilities. Is it sufficient to document this discrepancy in the commit message? Thanks, Vacha On Tue, Sep 2, 2025 at 6:45=E2=80=AFAM Peter Maydell wrote: > On Tue, 26 Aug 2025 at 19:50, Vacha Bhavsar > wrote: > > > > The QEMU GDB stub does not expose the ZA storage SME register to GDB vi= a > > the remote serial protocol, which can be a useful functionality to debu= g > SME > > code. To provide this functionality in Aarch64 target, this patch > registers the > > SME register set with the GDB stub. To do so, this patch implements the > > aarch64_gdb_get_sme_reg() and aarch64_gdb_set_sme_reg() functions to > > specify how to get and set the SME registers, and the > > arm_gen_dynamic_smereg_feature() function to generate the target > > description in XML format to indicate the target architecture supports > SME. > > Finally, this patch includes a dyn_smereg_feature structure to hold thi= s > > GDB XML description of the SME registers for each CPU. > > > > Signed-off-by: Vacha Bhavsar > > --- > > Changes since v5: > > - added code to handle the case when we have SME without SVE > > - added comments to indicate th cases in aarch64_gdb_get/set_sme_reg > > - added/removed braces where necessary > > - corrected capitalization in comments > > --- > > target/arm/cpu.h | 1 + > > target/arm/gdbstub.c | 9 ++- > > target/arm/gdbstub64.c | 121 +++++++++++++++++++++++++++++++++++++++++ > > target/arm/internals.h | 3 + > > 4 files changed, 133 insertions(+), 1 deletion(-) > > > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > > index dc9b6dce4c..8bd66d7049 100644 > > --- a/target/arm/cpu.h > > +++ b/target/arm/cpu.h > > @@ -933,6 +933,7 @@ struct ArchCPU { > > > > DynamicGDBFeatureInfo dyn_sysreg_feature; > > DynamicGDBFeatureInfo dyn_svereg_feature; > > + DynamicGDBFeatureInfo dyn_smereg_feature; > > DynamicGDBFeatureInfo dyn_m_systemreg_feature; > > DynamicGDBFeatureInfo dyn_m_secextreg_feature; > > > > diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c > > index ce4497ad7c..110258ec18 100644 > > --- a/target/arm/gdbstub.c > > +++ b/target/arm/gdbstub.c > > @@ -527,7 +527,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU > *cpu) > > * registers so we don't need to include both. > > */ > > #ifdef TARGET_AARCH64 > > - if (isar_feature_aa64_sve(&cpu->isar)) { > > + if (isar_feature_aa64_sve(&cpu->isar) || > isar_feature_aa64_sme(&cpu->isar)) { > > GDBFeature *feature =3D arm_gen_dynamic_svereg_feature(cs, > cs->gdb_num_regs); > > gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg, > > aarch64_gdb_set_sve_reg, feature, > 0); > > @@ -537,6 +537,13 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU > *cpu) > > > gdb_find_static_feature("aarch64-fpu.xml"), > > 0); > > } > > + > > + if (isar_feature_aa64_sme(&cpu->isar)) { > > + GDBFeature *sme_feature =3D arm_gen_dynamic_smereg_feature= (cs, > > + cs->gdb_num_regs); > > Your indent here and below for function calls on multiple > lines is wrong -- follow the way the existing code does it, > where the second line lines up with the first argument > after the '('. (We sometimes make an exception where the wrapping > would look terrible, but this is the usual approach.) > > > + gdb_register_coprocessor(cs, aarch64_gdb_get_sme_reg, > > + aarch64_gdb_set_sme_reg, sme_feature, 0); > > + } > > /* > > * Note that we report pauth information via the feature name > > * org.gnu.gdb.aarch64.pauth_v2, not org.gnu.gdb.aarch64.pauth= . > > diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c > > index 08e2858539..d3fd94b93d 100644 > > --- a/target/arm/gdbstub64.c > > +++ b/target/arm/gdbstub64.c > > @@ -249,6 +249,90 @@ int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t > *buf, int reg) > > return 0; > > } > > > > +int aarch64_gdb_get_sme_reg(CPUState *cs, GByteArray *buf, int reg) > > +{ > > + ARMCPU *cpu =3D ARM_CPU(cs); > > + CPUARMState *env =3D &cpu->env; > > + > > + switch (reg) { > > + case 0: /* svg register */ > > + { > > + int vq =3D 0; > > + if (FIELD_EX64(env->svcr, SVCR, SM)) { > > + vq =3D sve_vqm1_for_el_sm(env, arm_current_el(env), > > + FIELD_EX64(env->svcr, SVCR, SM)) + 1; > > + } > > + /* svg =3D vector granules (2 * vector quardwords) in streamin= g > mode */ > > + return gdb_get_reg64(buf, vq * 2); > > + } > > + case 1: /* svcr register */ > > + return gdb_get_reg64(buf, env->svcr); > > + case 2: /* za register */ > > + { > > + int len =3D 0; > > + int vq =3D cpu->sme_max_vq; > > + int svl =3D vq * 16; > > + for (int i =3D 0; i < svl; i++) { > > + for (int q =3D 0; q < vq; q++) { > > + len +=3D gdb_get_reg128(buf, > > + env->za_state.za[i].d[q * 2 + 1], > > + env->za_state.za[i].d[q * 2]); > > + } > > + } > > + return len; > > + } > > + default: > > + /* gdbstub asked for something out of range */ > > + qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", > __func__, reg); > > + break; > > + } > > + > > + return 0; > > +} > > + > > +int aarch64_gdb_set_sme_reg(CPUState *cs, uint8_t *buf, int reg) > > +{ > > + ARMCPU *cpu =3D ARM_CPU(cs); > > + CPUARMState *env =3D &cpu->env; > > + > > + switch (reg) { > > + case 0: /* svg register */ > > + /* cannot set svg via gdbstub */ > > + return 8; > > + case 1: /* svcr register */ > > + aarch64_set_svcr(env, ldq_le_p(buf), > > + R_SVCR_SM_MASK | R_SVCR_ZA_MASK); > > + return 8; > > + case 2: /* za register */ > > + { > > + int len =3D 0; > > + int vq =3D cpu->sme_max_vq; > > + int svl =3D vq * 16; > > + for (int i =3D 0; i < svl; i++) { > > + for (int q =3D 0; q < vq; q++) { > > + if (target_big_endian()) { > > + env->za_state.za[i].d[q * 2 + 1] =3D ldq_p(buf); > > + buf +=3D 8; > > + env->za_state.za[i].d[q * 2] =3D ldq_p(buf); > > + } else{ > > + env->za_state.za[i].d[q * 2] =3D ldq_p(buf); > > + buf +=3D 8; > > + env->za_state.za[i].d[q * 2 + 1] =3D ldq_p(buf); > > + } > > + buf +=3D 8; > > + len +=3D 16; > > + } > > + } > > + return len; > > + } > > + default: > > + /* gdbstub asked for something out of range */ > > + break; > > + } > > + > > + return 0; > > +} > > + > > int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg) > > { > > ARMCPU *cpu =3D ARM_CPU(cs); > > @@ -413,6 +497,43 @@ GDBFeature *arm_gen_dynamic_svereg_feature(CPUStat= e > *cs, int base_reg) > > return &cpu->dyn_svereg_feature.desc; > > } > > > > +GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *cs, int base_reg) > > +{ > > + ARMCPU *cpu =3D ARM_CPU(cs); > > + int vq =3D cpu->sme_max_vq; > > + int svl =3D vq * 16; > > + GDBFeatureBuilder builder; > > + int reg =3D 0; > > + > > + gdb_feature_builder_init(&builder, &cpu->dyn_smereg_feature.desc, > > + "org.gnu.gdb.aarch64.sme", "sme-registers.xml", base_reg); > > + > > + > > + /* Create the sme_bv vector type. */ > > + gdb_feature_builder_append_tag(&builder, > > + "", > > + svl); > > + > > + /* Create the sme_bvv vector type. */ > > + gdb_feature_builder_append_tag( > > + &builder, " count=3D\"%d\"/>", > > + svl); > > > https://sourceware.org/gdb/current/onlinedocs/gdb.html/AArch64-Features.h= tml#AArch64-Features > > says ZA should be a vector of bytes, not a vector of a vector of bytes. > Is it wrong ? > > > + > > + /* Define the svg, svcr, and za registers. */ > > + > > + /* fpscr & status registers */ > > This comment seems to be wrong and can be deleted. > > > + gdb_feature_builder_append_reg(&builder, "svg", 64, reg++, > > + "int", NULL); > > + gdb_feature_builder_append_reg(&builder, "svcr", 64, reg++, > > + "int", NULL); > > + gdb_feature_builder_append_reg(&builder, "za", svl * svl * 8, reg+= +, > > + "sme_bvv", NULL); > > We will also want to have support for the org.gnu.gdb.aarch64.sme2 > feature (which has the ZT0 register), but we can add that as > a separate patch later. > > > + > > + gdb_feature_builder_end(&builder); > > + > > + return &cpu->dyn_smereg_feature.desc; > > +} > > + > > #ifdef CONFIG_USER_ONLY > > int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg= ) > > { > > thanks > -- PMM > --000000000000a50d0c063dd52710 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi,

Regarding the definition of ZA as a= 'vector of bytes' in the gdb
documentation, the choice t= hat we have made in representing it
as a vector of vectors of byt= es is based on the xml retrieved by=C2=A0
the native gdb client w= hen run on a host with SME capabilities.

Is it suf= ficient to document this discrepancy in the commit message?

<= /div>
Thanks,
Vacha


=
On Tue, Sep 2, 2025 at 6:45=E2=80=AFAM Peter Maydell <peter.maydell@linaro.org> = wrote:
On Tue, 2= 6 Aug 2025 at 19:50, Vacha Bhavsar
<vac= ha.bhavsar@oss.qualcomm.com> wrote:
>
> The QEMU GDB stub does not expose the ZA storage SME register to GDB v= ia
> the remote serial protocol, which can be a useful functionality to deb= ug SME
> code. To provide this functionality in Aarch64 target, this patch regi= sters the
> SME register set with the GDB stub. To do so, this patch implements th= e
> aarch64_gdb_get_sme_reg() and aarch64_gdb_set_sme_reg() functions to > specify how to get and set the SME registers, and the
> arm_gen_dynamic_smereg_feature() function to generate the target
> description in XML format to indicate the target architecture supports= SME.
> Finally, this patch includes a dyn_smereg_feature structure to hold th= is
> GDB XML description of the SME registers for each CPU.
>
> Signed-off-by: Vacha Bhavsar <vacha.bhavsar@oss.qualcomm.com>
> ---
> Changes since v5:
> - added code to handle the case when we have SME without SVE
> - added comments to indicate th cases in aarch64_gdb_get/set_sme_reg > - added/removed braces where necessary
> - corrected capitalization in comments
> ---
>=C2=A0 target/arm/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A01 +
>=C2=A0 target/arm/gdbstub.c=C2=A0 =C2=A0|=C2=A0 =C2=A09 ++-
>=C2=A0 target/arm/gdbstub64.c | 121 +++++++++++++++++++++++++++++++++++= ++++++
>=C2=A0 target/arm/internals.h |=C2=A0 =C2=A03 +
>=C2=A0 4 files changed, 133 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index dc9b6dce4c..8bd66d7049 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -933,6 +933,7 @@ struct ArchCPU {
>
>=C2=A0 =C2=A0 =C2=A0 DynamicGDBFeatureInfo dyn_sysreg_feature;
>=C2=A0 =C2=A0 =C2=A0 DynamicGDBFeatureInfo dyn_svereg_feature;
> +=C2=A0 =C2=A0 DynamicGDBFeatureInfo dyn_smereg_feature;
>=C2=A0 =C2=A0 =C2=A0 DynamicGDBFeatureInfo dyn_m_systemreg_feature;
>=C2=A0 =C2=A0 =C2=A0 DynamicGDBFeatureInfo dyn_m_secextreg_feature;
>
> diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
> index ce4497ad7c..110258ec18 100644
> --- a/target/arm/gdbstub.c
> +++ b/target/arm/gdbstub.c
> @@ -527,7 +527,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU= *cpu)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* registers so we don't ne= ed to include both.
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
>=C2=A0 #ifdef TARGET_AARCH64
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (isar_feature_aa64_sve(&cpu->is= ar)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (isar_feature_aa64_sve(&cpu->is= ar) || isar_feature_aa64_sme(&cpu->isar)) {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 GDBFeature *feature = =3D arm_gen_dynamic_svereg_feature(cs, cs->gdb_num_regs);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 gdb_register_coprocess= or(cs, aarch64_gdb_get_sve_reg,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0aarch6= 4_gdb_set_sve_reg, feature, 0);
> @@ -537,6 +537,13 @@ void arm_cpu_register_gdb_regs_for_features(ARMCP= U *cpu)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gdb_fi= nd_static_feature("aarch64-fpu.xml"),
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00); >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (isar_feature_aa64_sme(&cpu->is= ar)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 GDBFeature *sme_feature =3D= arm_gen_dynamic_smereg_feature(cs,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cs->gdb_nu= m_regs);

Your indent here and below for function calls on multiple
lines is wrong -- follow the way the existing code does it,
where the second line lines up with the first argument
after the '('.=C2=A0 (We sometimes make an exception where the wrap= ping
would look terrible, but this is the usual approach.)

> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 gdb_register_coprocessor(cs= , aarch64_gdb_get_sme_reg,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 aarch64_gdb_s= et_sme_reg, sme_feature, 0);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /*
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* Note that we report pauth in= formation via the feature name
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* org.gnu.gdb.aarch64.pauth_v2= , not org.gnu.gdb.aarch64.pauth.
> diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
> index 08e2858539..d3fd94b93d 100644
> --- a/target/arm/gdbstub64.c
> +++ b/target/arm/gdbstub64.c
> @@ -249,6 +249,90 @@ int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t= *buf, int reg)
>=C2=A0 =C2=A0 =C2=A0 return 0;
>=C2=A0 }
>
> +int aarch64_gdb_get_sme_reg(CPUState *cs, GByteArray *buf, int reg) > +{
> +=C2=A0 =C2=A0 ARMCPU *cpu =3D ARM_CPU(cs);
> +=C2=A0 =C2=A0 CPUARMState *env =3D &cpu->env;
> +
> +=C2=A0 =C2=A0 switch (reg) {
> +=C2=A0 =C2=A0 case 0: /* svg register */
> +=C2=A0 =C2=A0 {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 int vq =3D 0;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (FIELD_EX64(env->svcr, SVCR, SM)) {=
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 vq =3D sve_vqm1_for_el_sm(e= nv, arm_current_el(env),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0FIELD_EX64(env->svcr, SVCR, SM)) + 1;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* svg =3D vector granules (2 * vector qu= ardwords) in streaming mode */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return gdb_get_reg64(buf, vq * 2);
> +=C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 case 1: /* svcr register */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return gdb_get_reg64(buf, env->svcr);<= br> > +=C2=A0 =C2=A0 case 2: /* za register */
> +=C2=A0 =C2=A0 {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 int len =3D 0;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 int vq =3D cpu->sme_max_vq;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 int svl =3D vq * 16;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 for (int i =3D 0; i < svl; i++) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 for (int q =3D 0; q < vq= ; q++) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 len +=3D gdb_= get_reg128(buf,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0env->za_state.za[i].d[q * 2 + 1],
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0env->za_state.za[i].d[q * 2]);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return len;
> +=C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 default:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* gdbstub asked for something out of ran= ge */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_log_mask(LOG_UNIMP, "%s: out of= range register %d", __func__, reg);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 return 0;
> +}
> +
> +int aarch64_gdb_set_sme_reg(CPUState *cs, uint8_t *buf, int reg)
> +{
> +=C2=A0 =C2=A0 ARMCPU *cpu =3D ARM_CPU(cs);
> +=C2=A0 =C2=A0 CPUARMState *env =3D &cpu->env;
> +
> +=C2=A0 =C2=A0 switch (reg) {
> +=C2=A0 =C2=A0 case 0: /* svg register */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* cannot set svg via gdbstub */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return 8;
> +=C2=A0 =C2=A0 case 1: /* svcr register */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 aarch64_set_svcr(env, ldq_le_p(buf),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 R_SVCR_SM_MASK | R_SVCR_ZA_= MASK);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return 8;
> +=C2=A0 =C2=A0 case 2: /* za register */
> +=C2=A0 =C2=A0 {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 int len =3D 0;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 int vq =3D cpu->sme_max_vq;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 int svl =3D vq * 16;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 for (int i =3D 0; i < svl; i++) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 for (int q =3D 0; q < vq= ; q++) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (target_bi= g_endian()) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= env->za_state.za[i].d[q * 2 + 1] =3D ldq_p(buf);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= buf +=3D 8;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= env->za_state.za[i].d[q * 2] =3D ldq_p(buf);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 } else{
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= env->za_state.za[i].d[q * 2] =3D ldq_p(buf);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= buf +=3D 8;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= env->za_state.za[i].d[q * 2 + 1] =3D ldq_p(buf);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 buf +=3D 8; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 len +=3D 16;<= br> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return len;
> +=C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 default:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* gdbstub asked for something out of ran= ge */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 return 0;
> +}
> +
>=C2=A0 int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int= reg)
>=C2=A0 {
>=C2=A0 =C2=A0 =C2=A0 ARMCPU *cpu =3D ARM_CPU(cs);
> @@ -413,6 +497,43 @@ GDBFeature *arm_gen_dynamic_svereg_feature(CPUSta= te *cs, int base_reg)
>=C2=A0 =C2=A0 =C2=A0 return &cpu->dyn_svereg_feature.desc;
>=C2=A0 }
>
> +GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *cs, int base_reg= )
> +{
> +=C2=A0 =C2=A0 ARMCPU *cpu =3D ARM_CPU(cs);
> +=C2=A0 =C2=A0 int vq =3D cpu->sme_max_vq;
> +=C2=A0 =C2=A0 int svl =3D vq * 16;
> +=C2=A0 =C2=A0 GDBFeatureBuilder builder;
> +=C2=A0 =C2=A0 int reg =3D 0;
> +
> +=C2=A0 =C2=A0 gdb_feature_builder_init(&builder, &cpu->dyn= _smereg_feature.desc,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 "org.gnu.gdb.aarch64.sme", &quo= t;sme-registers.xml", base_reg);
> +
> +
> +=C2=A0 =C2=A0 /* Create the sme_bv vector type. */
> +=C2=A0 =C2=A0 gdb_feature_builder_append_tag(&builder,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 "<vector id=3D\"sme_bv\"= ; type=3D\"uint8\" count=3D\"%d\"/>",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 svl);
> +
> +=C2=A0 =C2=A0 /* Create the sme_bvv vector type. */
> +=C2=A0 =C2=A0 gdb_feature_builder_append_tag(
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 &builder, "<vector id=3D\&quo= t;sme_bvv\" type=3D\"sme_bv\" count=3D\"%d\"/>&= quot;,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 svl);

https:/= /sourceware.org/gdb/current/onlinedocs/gdb.html/AArch64-Features.html#AArch= 64-Features

says ZA should be a vector of bytes, not a vector of a vector of bytes.
Is it wrong ?

> +
> +=C2=A0 =C2=A0 /* Define the svg, svcr, and za registers. */
> +
> +=C2=A0 =C2=A0 /* fpscr & status registers */

This comment seems to be wrong and can be deleted.

> +=C2=A0 =C2=A0 gdb_feature_builder_append_reg(&builder, "svg&= quot;, 64, reg++,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 "int", NULL);
> +=C2=A0 =C2=A0 gdb_feature_builder_append_reg(&builder, "svcr= ", 64, reg++,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 "int", NULL);
> +=C2=A0 =C2=A0 gdb_feature_builder_append_reg(&builder, "za&q= uot;, svl * svl * 8, reg++,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 "sme_bvv", NULL);

We will also want to have support for the org.gnu.gdb.aarch64.sme2
feature (which has the ZT0 register), but we can add that as
a separate patch later.

> +
> +=C2=A0 =C2=A0 gdb_feature_builder_end(&builder);
> +
> +=C2=A0 =C2=A0 return &cpu->dyn_smereg_feature.desc;
> +}
> +
>=C2=A0 #ifdef CONFIG_USER_ONLY
>=C2=A0 int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, i= nt reg)
>=C2=A0 {

thanks
-- PMM
--000000000000a50d0c063dd52710--