* [PATCH v8 1/3] target/arm: Increase MAX_PACKET_LENGTH for SME ZA remote gdb debugging
2025-09-09 16:10 [PATCH v8 0/3] target/arm: Added support for SME register exposure to GDB Vacha Bhavsar
@ 2025-09-09 16:10 ` Vacha Bhavsar
2025-09-09 16:10 ` [PATCH v8 2/3] target/arm: Added support for SME register exposure to GDB Vacha Bhavsar
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Vacha Bhavsar @ 2025-09-09 16:10 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, Thomas Huth, Philippe Mathieu-Daudé,
Peter Maydell, Paolo Bonzini, qemu-arm, Vacha Bhavsar
This patch increases the value of the MAX_PACKET_LEGNTH to
131104 from 4096 to allow the GDBState.line_buf to be large enough
to accommodate the full contents of the SME ZA storage when the
vector length is maximal. This is in preparation for a related
patch that allows SME register visibility through remote GDB
debugging.
Signed-off-by: Vacha Bhavsar <vacha.bhavsar@oss.qualcomm.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
Changes since v4:
- the value for MAX_PACKET_LENGTH is changed from 131100 to
131104 to align with a similar update made to gdbserver
---
gdbstub/internals.h | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/gdbstub/internals.h b/gdbstub/internals.h
index bf5a5c6302..87f64b6318 100644
--- a/gdbstub/internals.h
+++ b/gdbstub/internals.h
@@ -11,7 +11,27 @@
#include "exec/cpu-common.h"
-#define MAX_PACKET_LENGTH 4096
+/*
+* Most "large" transfers (e.g. memory reads, feature XML
+* transfer) have mechanisms in the gdb protocol for splitting
+* them. However, register values in particular cannot currently
+* be split. This packet size must therefore be at least big enough
+* for the worst-case register size. Currently that is Arm SME
+* ZA storage with a 256x256 byte value. We also must account
+* for the conversion from raw data to hex in gdb_memtohex(),
+* which writes 2 * size bytes, and for other protocol overhead
+* including command, register number and checksum which add
+* another 4 bytes of overhead. However, to be consistent with
+* the changes made in gdbserver to address this same requirement,
+* we add a total of 32 bytes to account for protocol overhead
+* (unclear why specifically 32 bytes), bringing the value of
+* MAX_PACKET_LENGTH to 2 * 256 * 256 + 32 = 131104.
+*
+* The commit making this change for gdbserver can be found here:
+* https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=
+* b816042e88583f280ad186ff124ab84d31fb592b
+*/
+#define MAX_PACKET_LENGTH 131104
/*
* Shared structures and definitions
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v8 2/3] target/arm: Added support for SME register exposure to GDB
2025-09-09 16:10 [PATCH v8 0/3] target/arm: Added support for SME register exposure to GDB Vacha Bhavsar
2025-09-09 16:10 ` [PATCH v8 1/3] target/arm: Increase MAX_PACKET_LENGTH for SME ZA remote gdb debugging Vacha Bhavsar
@ 2025-09-09 16:10 ` Vacha Bhavsar
2025-09-09 16:10 ` [PATCH v8 3/3] target/arm: Added test case " Vacha Bhavsar
2025-09-16 10:39 ` [PATCH v8 0/3] target/arm: Added support " Peter Maydell
3 siblings, 0 replies; 6+ messages in thread
From: Vacha Bhavsar @ 2025-09-09 16:10 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, Thomas Huth, Philippe Mathieu-Daudé,
Peter Maydell, Paolo Bonzini, qemu-arm, Vacha Bhavsar
The QEMU GDB stub does not expose the ZA storage SME register to GDB via
the remote serial protocol, which can be a useful functionality to debug SME
code. To provide this functionality in Aarch64 target, this patch registers the
SME register set with the GDB stub. To do so, this patch implements the
aarch64_gdb_get_sme_reg() and aarch64_gdb_set_sme_reg() functions to
specify how to get and set the SME registers, and the
arm_gen_dynamic_smereg_feature() function to generate the target
description in XML format to indicate the target architecture supports SME.
Finally, this patch includes a dyn_smereg_feature structure to hold this
GDB XML description of the SME registers for each CPU.
Note that according to the GDB documentation the ZA register is defined as a
vector of bytes, however the target description xml retrieved when using gdb
natively on a host with SME capabilities represents the ZA register as a vector
of vectors of bytes. To remain consistent with this implementation this patch
also represents the ZA register as a vector of vectors of bytes as is done by
GDB here:
https://github.com/bminor/binutils-gdb/blob/5cce2b7006daa7073b98e3d1a3b176199d1381d7/gdb/features/aarch64-sme.c#L50
Signed-off-by: Vacha Bhavsar <vacha.bhavsar@oss.qualcomm.com>
---
Changes since v6:
- removed unnecessary comment
- corrected indentation
---
target/arm/cpu.h | 1 +
target/arm/gdbstub.c | 9 +++-
target/arm/gdbstub64.c | 119 +++++++++++++++++++++++++++++++++++++++++
target/arm/internals.h | 3 ++
4 files changed, 131 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c15d79a106..92808c2fe6 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -935,6 +935,7 @@ struct ArchCPU {
DynamicGDBFeatureInfo dyn_sysreg_feature;
DynamicGDBFeatureInfo dyn_svereg_feature;
+ DynamicGDBFeatureInfo dyn_smereg_feature;
DynamicGDBFeatureInfo dyn_m_systemreg_feature;
DynamicGDBFeatureInfo dyn_m_secextreg_feature;
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index ce4497ad7c..cfde7c3a46 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -527,7 +527,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
* registers so we don't need to include both.
*/
#ifdef TARGET_AARCH64
- if (isar_feature_aa64_sve(&cpu->isar)) {
+ if (isar_feature_aa64_sve(&cpu->isar) || isar_feature_aa64_sme(&cpu->isar)) {
GDBFeature *feature = arm_gen_dynamic_svereg_feature(cs, cs->gdb_num_regs);
gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg,
aarch64_gdb_set_sve_reg, feature, 0);
@@ -537,6 +537,13 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
gdb_find_static_feature("aarch64-fpu.xml"),
0);
}
+
+ if (isar_feature_aa64_sme(&cpu->isar)) {
+ GDBFeature *sme_feature = arm_gen_dynamic_smereg_feature(cs,
+ cs->gdb_num_regs);
+ gdb_register_coprocessor(cs, aarch64_gdb_get_sme_reg,
+ aarch64_gdb_set_sme_reg, sme_feature, 0);
+ }
/*
* Note that we report pauth information via the feature name
* org.gnu.gdb.aarch64.pauth_v2, not org.gnu.gdb.aarch64.pauth.
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index 08e2858539..3bccde2bf2 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -249,6 +249,90 @@ int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg)
return 0;
}
+int aarch64_gdb_get_sme_reg(CPUState *cs, GByteArray *buf, int reg)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
+ switch (reg) {
+ case 0: /* svg register */
+ {
+ int vq = 0;
+ if (FIELD_EX64(env->svcr, SVCR, SM)) {
+ vq = sve_vqm1_for_el_sm(env, arm_current_el(env),
+ FIELD_EX64(env->svcr, SVCR, SM)) + 1;
+ }
+ /* svg = vector granules (2 * vector quardwords) in streaming mode */
+ return gdb_get_reg64(buf, vq * 2);
+ }
+ case 1: /* svcr register */
+ return gdb_get_reg64(buf, env->svcr);
+ case 2: /* za register */
+ {
+ int len = 0;
+ int vq = cpu->sme_max_vq;
+ int svl = vq * 16;
+ for (int i = 0; i < svl; i++) {
+ for (int q = 0; q < vq; q++) {
+ len += gdb_get_reg128(buf,
+ env->za_state.za[i].d[q * 2 + 1],
+ env->za_state.za[i].d[q * 2]);
+ }
+ }
+ return len;
+ }
+ default:
+ /* gdbstub asked for something out of range */
+ qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg);
+ break;
+ }
+
+ return 0;
+}
+
+int aarch64_gdb_set_sme_reg(CPUState *cs, uint8_t *buf, int reg)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
+ switch (reg) {
+ case 0: /* svg register */
+ /* cannot set svg via gdbstub */
+ return 8;
+ case 1: /* svcr register */
+ aarch64_set_svcr(env, ldq_le_p(buf),
+ R_SVCR_SM_MASK | R_SVCR_ZA_MASK);
+ return 8;
+ case 2: /* za register */
+ {
+ int len = 0;
+ int vq = cpu->sme_max_vq;
+ int svl = vq * 16;
+ for (int i = 0; i < svl; i++) {
+ for (int q = 0; q < vq; q++) {
+ if (target_big_endian()) {
+ env->za_state.za[i].d[q * 2 + 1] = ldq_p(buf);
+ buf += 8;
+ env->za_state.za[i].d[q * 2] = ldq_p(buf);
+ } else{
+ env->za_state.za[i].d[q * 2] = ldq_p(buf);
+ buf += 8;
+ env->za_state.za[i].d[q * 2 + 1] = ldq_p(buf);
+ }
+ buf += 8;
+ len += 16;
+ }
+ }
+ return len;
+ }
+ default:
+ /* gdbstub asked for something out of range */
+ break;
+ }
+
+ return 0;
+}
+
int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg)
{
ARMCPU *cpu = ARM_CPU(cs);
@@ -413,6 +497,41 @@ GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cs, int base_reg)
return &cpu->dyn_svereg_feature.desc;
}
+GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *cs, int base_reg)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ int vq = cpu->sme_max_vq;
+ int svl = vq * 16;
+ GDBFeatureBuilder builder;
+ int reg = 0;
+
+ gdb_feature_builder_init(&builder, &cpu->dyn_smereg_feature.desc,
+ "org.gnu.gdb.aarch64.sme", "sme-registers.xml",
+ base_reg);
+
+
+ /* Create the sme_bv vector type. */
+ gdb_feature_builder_append_tag(
+ &builder, "<vector id=\"sme_bv\" type=\"uint8\" count=\"%d\"/>",
+ svl);
+
+ /* Create the sme_bvv vector type. */
+ gdb_feature_builder_append_tag(
+ &builder, "<vector id=\"sme_bvv\" type=\"sme_bv\" count=\"%d\"/>",
+ svl);
+
+ /* Define the svg, svcr, and za registers. */
+
+ gdb_feature_builder_append_reg(&builder, "svg", 64, reg++, "int", NULL);
+ gdb_feature_builder_append_reg(&builder, "svcr", 64, reg++, "int", NULL);
+ gdb_feature_builder_append_reg(&builder, "za", svl * svl * 8, reg++,
+ "sme_bvv", NULL);
+
+ gdb_feature_builder_end(&builder);
+
+ return &cpu->dyn_smereg_feature.desc;
+}
+
#ifdef CONFIG_USER_ONLY
int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg)
{
diff --git a/target/arm/internals.h b/target/arm/internals.h
index f5a1e75db3..df99a17448 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1820,8 +1820,11 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
}
GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg);
+GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *cpu, int base_reg);
int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg);
int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg);
+int aarch64_gdb_get_sme_reg(CPUState *cs, GByteArray *buf, int reg);
+int aarch64_gdb_set_sme_reg(CPUState *cs, uint8_t *buf, int reg);
int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *buf, int reg);
int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg);
int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg);
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v8 3/3] target/arm: Added test case for SME register exposure to GDB
2025-09-09 16:10 [PATCH v8 0/3] target/arm: Added support for SME register exposure to GDB Vacha Bhavsar
2025-09-09 16:10 ` [PATCH v8 1/3] target/arm: Increase MAX_PACKET_LENGTH for SME ZA remote gdb debugging Vacha Bhavsar
2025-09-09 16:10 ` [PATCH v8 2/3] target/arm: Added support for SME register exposure to GDB Vacha Bhavsar
@ 2025-09-09 16:10 ` Vacha Bhavsar
2025-09-16 10:39 ` [PATCH v8 0/3] target/arm: Added support " Peter Maydell
3 siblings, 0 replies; 6+ messages in thread
From: Vacha Bhavsar @ 2025-09-09 16:10 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, Thomas Huth, Philippe Mathieu-Daudé,
Peter Maydell, Paolo Bonzini, qemu-arm, Vacha Bhavsar
This patch adds a test case to test SME register exposure to
a remote gdb debugging session. This test simply sets and
reads SME registers.
Signed-off-by: Vacha Bhavsar <vacha.bhavsar@oss.qualcomm.com>
---
Changes since v7:
- removed int casting in test and removed checks for appropriate
gdb versions which support the required int casting
- merged quadword and doubleword tile slice support test into a
single tile slice support test
---
configure | 6 ++
tests/tcg/aarch64/Makefile.target | 29 +++++++
tests/tcg/aarch64/gdbstub/test-sme.py | 116 ++++++++++++++++++++++++++
3 files changed, 151 insertions(+)
create mode 100644 tests/tcg/aarch64/gdbstub/test-sme.py
diff --git a/configure b/configure
index 274a778764..9aea02cf6a 100755
--- a/configure
+++ b/configure
@@ -1839,6 +1839,12 @@ for target in $target_list; do
echo "GDB=$gdb_bin" >> $config_target_mak
fi
+ if test "${gdb_arches#*$arch}" != "$gdb_arches" && version_ge $gdb_version 14.1; then
+ echo "GDB_HAS_SME_TILES=y" >> $config_target_mak
+ else
+ echo "GDB_HAS_SME_TILES=n" >> $config_target_mak
+ fi
+
if test "${gdb_arches#*aarch64}" != "$gdb_arches" && version_ge $gdb_version 15.1; then
echo "GDB_HAS_MTE=y" >> $config_target_mak
fi
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index 16ddcf4f88..41b31c9353 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -134,6 +134,35 @@ run-gdbstub-sve-ioctls: sve-ioctls
EXTRA_RUNS += run-gdbstub-sysregs run-gdbstub-sve-ioctls
+ifneq ($(CROSS_AS_HAS_ARMV9_SME),)
+# SME gdbstub tests
+
+run-gdbstub-sysregs-sme: sysregs
+ $(call run-test, $@, $(GDB_SCRIPT) \
+ --gdb $(GDB) \
+ --qemu $(QEMU) --qargs "$(QEMU_OPTS)" \
+ --bin $< --test $(AARCH64_SRC)/gdbstub/test-sme.py \
+ -- test_sme --gdb_basic_za_test, \
+ basic gdbstub SME support)
+
+ifeq ($(GDB_HAS_SME_TILES),y)
+run-gdbstub-sysregs-sme-tile-slice: sysregs
+ $(call run-test, $@, $(GDB_SCRIPT) \
+ --gdb $(GDB) \
+ --qemu $(QEMU) --qargs "$(QEMU_OPTS)" \
+ --bin $< --test $(AARCH64_SRC)/gdbstub/test-sme.py \
+ -- test_sme --gdb_tile_slice_test, \
+ gdbstub SME ZA tile slice support)
+else
+run-gdbstub-sysregs-sme-tile-slice: sysregs
+ $(call skip-test,"gdbstub SME ZA tile slice support", \
+ "selected gdb ($(GDB)) does not support SME ZA tile slices")
+endif
+
+EXTRA_RUNS += run-gdbstub-sysregs-sme run-gdbstub-sysregs-sme-tile-slice
+
+endif
+
ifeq ($(GDB_HAS_MTE),y)
run-gdbstub-mte: mte-8
$(call run-test, $@, $(GDB_SCRIPT) \
diff --git a/tests/tcg/aarch64/gdbstub/test-sme.py b/tests/tcg/aarch64/gdbstub/test-sme.py
new file mode 100644
index 0000000000..ef3a4fcaee
--- /dev/null
+++ b/tests/tcg/aarch64/gdbstub/test-sme.py
@@ -0,0 +1,116 @@
+#
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+from __future__ import print_function
+#
+# Test the SME registers are visible and changeable via gdbstub
+#
+# This is launched via tests/guest-debug/run-test.py
+#
+
+import argparse
+import gdb
+from test_gdbstub import main, report
+
+MAGIC = 0x01020304
+BASIC_ZA_TEST = 0
+TILE_SLICE_TEST = 0
+
+def run_test():
+
+ # Run the requested test(s) for SME ZA gdbstub support
+
+ if BASIC_ZA_TEST:
+ run_basic_sme_za_gdbstub_support_test()
+ if TILE_SLICE_TEST:
+ run_basic_sme_za_tile_slice_gdbstub_support_test()
+
+def run_basic_sme_za_gdbstub_support_test():
+
+ # This test will check for gdbstub support for correctly reading
+ # and writing to the SME ZA register at the byte level.
+
+ frame = gdb.selected_frame()
+ rname = "za"
+ za = frame.read_register(rname)
+ report(True, "Reading %s" % rname)
+
+ # Writing to the ZA register, byte by byte.
+ for i in range(0, 16):
+ for j in range(0, 16):
+ cmd = "set $za[%d][%d] = 0x01" % (i, j)
+ gdb.execute(cmd)
+ report(True, "%s" % cmd)
+
+ # Reading from the ZA register, byte by byte.
+ for i in range(0, 16):
+ for j in range(0, 16):
+ reg = "$za[%d][%d]" % (i, j)
+ v = gdb.parse_and_eval(reg)
+ report(str(v.type) == "uint8_t", "size of %s" % (reg))
+ report(v == 0x1, "%s is 0x%x" % (reg, 0x1))
+
+def run_basic_sme_za_tile_slice_gdbstub_support_test():
+
+ # Test if SME ZA tile slices, both horizontal and vertical,
+ # can be correctly read and written to. The sizes to test
+ # are quadwords and doublewords.
+
+ sizes = {}
+ sizes["q"] = "uint128_t"
+ sizes["d"] = "uint64_t"
+
+ # Accessing requested sizes of elements of ZA
+ for size in sizes:
+
+ # Accessing various ZA tiles
+ for i in range(0, 4):
+
+ # Accessing various horizontal slices for each ZA tile
+ for j in range(0, 4):
+ # Writing to various elements in each tile slice
+ for k in range(0, 4):
+ cmd = "set $za%dh%c%d[%d] = 0x%x" % (i, size, j, k, MAGIC)
+ gdb.execute(cmd)
+ report(True, "%s" % cmd)
+
+ # Reading from the written elements in each tile slice
+ for k in range(0, 4):
+ reg = "$za%dh%c%d[%d]" % (i, size, j, k)
+ v = gdb.parse_and_eval(reg)
+ report(str(v.type) == sizes[size], "size of %s" % (reg))
+ report(v == MAGIC, "%s is 0x%x" % (reg, MAGIC))
+
+ # Accessing various vertical slices for each ZA tile
+ for j in range(0, 4):
+ # Writing to various elements in each tile slice
+ for k in range(0, 4):
+ cmd = "set $za%dv%c%d[%d] = 0x%x" % (i, size, j, k, MAGIC)
+ gdb.execute(cmd)
+ report(True, "%s" % cmd)
+
+ # Reading from the written elements in each tile slice
+ for k in range(0, 4):
+ reg = "$za%dv%c%d[%d]" % (i, size, j, k)
+ v = gdb.parse_and_eval(reg)
+ report(str(v.type) == sizes[size], "size of %s" % (reg))
+ report(v == MAGIC, "%s is 0x%x" % (reg, MAGIC))
+
+
+parser = argparse.ArgumentParser(description="A gdbstub test for SME support")
+parser.add_argument("--gdb_basic_za_test",
+ help="Enable test for basic SME ZA support",
+ action="store_true")
+parser.add_argument("--gdb_tile_slice_test",
+ help="Enable test for ZA tile slice support",
+ action="store_true")
+args = parser.parse_args()
+
+if args.gdb_basic_za_test:
+ BASIC_ZA_TEST = 1
+if args.gdb_tile_slice_test:
+ TILE_SLICE_TEST = 1
+
+main(run_test, expected_arch="aarch64")
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v8 0/3] target/arm: Added support for SME register exposure to GDB
2025-09-09 16:10 [PATCH v8 0/3] target/arm: Added support for SME register exposure to GDB Vacha Bhavsar
` (2 preceding siblings ...)
2025-09-09 16:10 ` [PATCH v8 3/3] target/arm: Added test case " Vacha Bhavsar
@ 2025-09-16 10:39 ` Peter Maydell
2025-09-16 13:43 ` Vacha Bhavsar
3 siblings, 1 reply; 6+ messages in thread
From: Peter Maydell @ 2025-09-16 10:39 UTC (permalink / raw)
To: Vacha Bhavsar
Cc: qemu-devel, Alex Bennée, Thomas Huth,
Philippe Mathieu-Daudé, Paolo Bonzini, qemu-arm
On Tue, 9 Sept 2025 at 17:10, Vacha Bhavsar
<vacha.bhavsar@oss.qualcomm.com> wrote:
>
> The QEMU GDB stub does not expose the ZA storage SME register to GDB via
> the remote serial protocol, which can be a useful functionality to debug SME
> code. To provide this functionality in Aarch64 target, this patch registers the
> SME register set with the GDB stub. To do so, this patch implements the
> aarch64_gdb_get_sme_reg() and aarch64_gdb_set_sme_reg() functions to
> specify how to get and set the SME registers, and the
> arm_gen_dynamic_smereg_feature() function to generate the target
> description in XML format to indicate the target architecture supports SME.
> Finally, this patch includes a dyn_smereg_feature structure to hold this
> GDB XML description of the SME registers for each CPU.
>
> Additionally, this patch series increases the value of MAX_PACKET_LENGTH
> to allow for remote GDB debugging of the ZA register when the vector
> length is maximal.
>
> We have chosen to drop the patch related to changing GDBState's line_buf
> to a dynamically re-sizeable GString for the time being.
>
> This patch also includes a test case for testing SME register exposure
> to GDB, based off of the existing SVE test case for the gdbstub.
>
> Vacha Bhavsar (3):
> target/arm: Increase MAX_PACKET_LENGTH for SME ZA remote gdb debugging
> target/arm: Added support for SME register exposure to GDB
> target/arm: Added test case for SME register exposure to GDB
Thanks, I have applied this version to target-arm.next.
I had to fix up quite a few style nits reported by scripts/checkpatch.pl:
for future contributions I would suggest running your patches through
it. The script is not infallible so you have to use some judgement
in deciding whether to make changes, but it catches simple issues
like trailing whitespace or mixing tabs and spaces in indentation.
-- PMM
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v8 0/3] target/arm: Added support for SME register exposure to GDB
2025-09-16 10:39 ` [PATCH v8 0/3] target/arm: Added support " Peter Maydell
@ 2025-09-16 13:43 ` Vacha Bhavsar
0 siblings, 0 replies; 6+ messages in thread
From: Vacha Bhavsar @ 2025-09-16 13:43 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-devel, Alex Bennée, Thomas Huth,
Philippe Mathieu-Daudé, Paolo Bonzini, qemu-arm
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Noted, thank you!
On Tue, Sep 16, 2025 at 6:39 AM Peter Maydell <peter.maydell@linaro.org>
wrote:
> On Tue, 9 Sept 2025 at 17:10, Vacha Bhavsar
> <vacha.bhavsar@oss.qualcomm.com> wrote:
> >
> > The QEMU GDB stub does not expose the ZA storage SME register to GDB via
> > the remote serial protocol, which can be a useful functionality to debug
> SME
> > code. To provide this functionality in Aarch64 target, this patch
> registers the
> > SME register set with the GDB stub. To do so, this patch implements the
> > aarch64_gdb_get_sme_reg() and aarch64_gdb_set_sme_reg() functions to
> > specify how to get and set the SME registers, and the
> > arm_gen_dynamic_smereg_feature() function to generate the target
> > description in XML format to indicate the target architecture supports
> SME.
> > Finally, this patch includes a dyn_smereg_feature structure to hold this
> > GDB XML description of the SME registers for each CPU.
> >
> > Additionally, this patch series increases the value of MAX_PACKET_LENGTH
> > to allow for remote GDB debugging of the ZA register when the vector
> > length is maximal.
> >
> > We have chosen to drop the patch related to changing GDBState's line_buf
> > to a dynamically re-sizeable GString for the time being.
> >
> > This patch also includes a test case for testing SME register exposure
> > to GDB, based off of the existing SVE test case for the gdbstub.
> >
> > Vacha Bhavsar (3):
> > target/arm: Increase MAX_PACKET_LENGTH for SME ZA remote gdb debugging
> > target/arm: Added support for SME register exposure to GDB
> > target/arm: Added test case for SME register exposure to GDB
>
> Thanks, I have applied this version to target-arm.next.
>
> I had to fix up quite a few style nits reported by scripts/checkpatch.pl:
> for future contributions I would suggest running your patches through
> it. The script is not infallible so you have to use some judgement
> in deciding whether to make changes, but it catches simple issues
> like trailing whitespace or mixing tabs and spaces in indentation.
>
> -- PMM
>
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^ permalink raw reply [flat|nested] 6+ messages in thread