From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39061) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YqQ64-0008J8-DT for qemu-devel@nongnu.org; Thu, 07 May 2015 14:00:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YqQ5z-0006lr-SZ for qemu-devel@nongnu.org; Thu, 07 May 2015 14:00:32 -0400 Received: from mail-qk0-x232.google.com ([2607:f8b0:400d:c09::232]:34156) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YqQ5z-0006ln-Ov for qemu-devel@nongnu.org; Thu, 07 May 2015 14:00:27 -0400 Received: by qkgx75 with SMTP id x75so32852380qkg.1 for ; Thu, 07 May 2015 11:00:27 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: Date: Thu, 7 May 2015 15:00:26 -0300 Message-ID: From: aurelio remonda Content-Type: multipart/alternative; boundary=001a11c0b284bf0736051581af09 Subject: Re: [Qemu-devel] [ARM]: Adding support for Cortex-M4 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org --001a11c0b284bf0736051581af09 Content-Type: text/plain; charset=UTF-8 Im replying this cause i made a mistake asking to someones private mail, sorry: > OK, another question. How come if Cortex-M3 doesnt support DSP instructions > qemu understand them? I tried some of them with an stellaris lm3s6965evb. I > do understand that they were implemented for the A profile cores, but not > for M ones. Is this a bug or im missing something? If our cortex-m3 model doesn't fault on an instruction that's not implemented in the M3 then that's a bug, yes. If you provide more detail we can fix it. 2015-05-05 9:52 GMT-03:00 aurelio remonda : > Hi, i would like to to add support for cortex-m4 on qemu. Most features of > the Cortex-M3 and M4 are the same with the significant difference that > Cortex-M4 has DSP extensions and optional FPU. Even so, i really need some > pointers for this (im a newbie on qemu devel). I found out that qemu can > manage dsp instructions such as ADD16, ASX, SAX, etc. and all their > combinations with suffixes (u, s, sh, etc.), so half (if not all) of the > work is done. > > How should I go about this? What's the standard procedure for adding a new > CPU, even if it's so similar to the existing ones? That is, which are the > relevant functions/files that I should modify, and so on. > > Thanks a lot! > --001a11c0b284bf0736051581af09 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
Im replying this cause i made a mistake= asking to someones private mail, sorry:
> OK, another question. How = come if Cortex-M3 doesnt support DSP instructions
> qemu understand them? I tried some of them with an stellaris lm3s6965e= vb. I
> do understand that they were implemented for the A profile cores, but = not
> for M ones. Is this a bug or im missing something?

If our cortex-m3 model doesn't fault on an instruction that'= s not
implemented in the M3 then that's a bug, yes. If you provide more
detail we can fix it.

2015-05-05 9:52 GMT-03:00 aurelio remonda <<= a href=3D"mailto:aurelioremonda@gmail.com" target=3D"_blank">aurelioremonda= @gmail.com>:
Hi, i would like to to add support for cortex-m4 on qemu. Most feat= ures of the Cortex-M3 and M4 are the same with the significant difference t= hat Cortex-M4 has DSP extensions and optional FPU. Even so, i really need s= ome pointers for this (im a newbie on qemu devel). I found out that qemu ca= n manage dsp instructions such as ADD16, ASX, SAX, etc. and all their combi= nations with suffixes (u, s, sh, etc.), so half (if not all) of the work is= done.

How should I go about this? What's the standar= d procedure for adding a new CPU, even if it's so similar to the existi= ng ones? That is, which are the relevant functions/files that I should modi= fy, and so on.

Thanks a lot!

--001a11c0b284bf0736051581af09--