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d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=tA6JXnX1qvmGOHN0Ei6Kt61q6K0lbOTRSQpKYmuNw+Y=; b=M/HfTcixnvTwouqKrBCEodTeUq8x2r0dOzWnosEIGZPMQ7C4v5W0Qpc3sfS2qWP8OA 9BLVUJqqXirvlsPO7LdN/83JRtYH1UsSHAfMLzIg1u5ZVBcD0svrU036XnzTZgXB8HtO O4j0xpVJWKy3lAePsKJ3R6CaM0lvMzx31HfEzc3BP/aFT37k01In9idjs1thHd0g9Dj4 OHFY0dRnmBUjekGyTY7LXyhDtJUKq4A6OPtrmQRWMnJin9osRwTR8OCIpoS/U72jtVJm AIU9PRgBvpDH51lhG43EO+f9lZBNaeihbM3phuh8rJG1JaBSNK3VfFNy2Zjgt5LZqHC2 Cmgg== X-Gm-Message-State: AOAM530iWB9wvS3zQA9n8yOZbNMtFHQsQefa7FGT2Ck4Px7x+Tulnn3o es1lL0KdLB7nNGbAectkKJK9V2NCdGkkXNdJfW10zQ== X-Google-Smtp-Source: ABdhPJzj91QQfA99k7YDuyFt4wKnHyyAYGDQsDEUKZrTZ6iRW5U2wYvSc9fQyiXy+MxKusIw1o5D0AayEugrqVjISvw= X-Received: by 2002:a05:6602:2ac3:: with SMTP id m3mr9782767iov.138.1634453840740; Sat, 16 Oct 2021 23:57:20 -0700 (PDT) MIME-Version: 1.0 References: <20211015065500.3850513-1-frank.chang@sifive.com> <20211015065500.3850513-3-frank.chang@sifive.com> <4b718269-b222-c08f-ca72-656bacc31331@linaro.org> <2ac1b2bd-efa9-2005-5c0a-cace9346cbd7@linaro.org> In-Reply-To: From: Frank Chang Date: Sun, 17 Oct 2021 14:57:09 +0800 Message-ID: Subject: Re: [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax To: Richard Henderson Content-Type: multipart/alternative; boundary="0000000000009453d205ce86f021" Received-SPF: pass client-ip=2607:f8b0:4864:20::d2b; envelope-from=frank.chang@sifive.com; helo=mail-io1-xd2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Bin Meng , "qemu-devel@nongnu.org Developers" , Chih-Min Chao , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --0000000000009453d205ce86f021 Content-Type: text/plain; charset="UTF-8" On Sun, Oct 17, 2021 at 8:55 AM Frank Chang wrote: > On Sun, Oct 17, 2021 at 1:56 AM Richard Henderson < > richard.henderson@linaro.org> wrote: > >> On 10/16/21 1:52 AM, Frank Chang wrote: >> > On Sat, Oct 16, 2021 at 1:05 AM Richard Henderson < >> richard.henderson@linaro.org >> > > wrote: >> > >> > On 10/14/21 11:54 PM, frank.chang@sifive.com > frank.chang@sifive.com> wrote: >> > > From: Chih-Min Chao> chihmin.chao@sifive.com>> >> > > >> > > The sNaN propagation behavior has been changed since >> > > cd20cee7 inhttps://github.com/riscv/riscv-isa-manual >> > >> > > >> > > Signed-off-by: Chih-Min Chao> chihmin.chao@sifive.com>> >> > > --- >> > > target/riscv/fpu_helper.c | 8 ++++---- >> > > 1 file changed, 4 insertions(+), 4 deletions(-) >> > > >> > > diff --git a/target/riscv/fpu_helper.c >> b/target/riscv/fpu_helper.c >> > > index 8700516a14c..1472ead2528 100644 >> > > --- a/target/riscv/fpu_helper.c >> > > +++ b/target/riscv/fpu_helper.c >> > > @@ -174,14 +174,14 @@ uint64_t helper_fmin_s(CPURISCVState *env, >> uint64_t rs1, >> > uint64_t rs2) >> > > { >> > > float32 frs1 = check_nanbox_s(rs1); >> > > float32 frs2 = check_nanbox_s(rs2); >> > > - return nanbox_s(float32_minnum(frs1, frs2, >> &env->fp_status)); >> > > + return nanbox_s(float32_minnum_noprop(frs1, frs2, >> &env->fp_status)); >> > > } >> > >> > Don't you need to conditionalize behaviour on the isa revision? >> > >> > >> > I will pick the right API based on CPU privilege spec version. >> >> There's a separate F-extension revision number: 2.2. >> >> But I'll leave it up to those more knowledgeable about the revision >> combinations actually >> present in the field to decide. >> >> > I did some history searches on RISC-V ISA spec Github repo. > > F-extension was bumped to v2.2 at (2018/08/28): > > https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20180828-eb78171 > The privilege spec is v1.10-draft at the time. > > and later ratified at (2019/03/26): > > https://github.com/riscv/riscv-isa-manual/releases/tag/IMFDQC-Ratification-20190305 > > The spec was updated to use IEEE 754-2019 min/max functions in commit: > #cd20cee7 > > (2019/06/05). > Sorry, the commit date is 2017/06/05, not 2019/06/05. But I think it's probably easier and clearer to just introduce an extra *fext_ver* variable. We can set CPUs which are Privilege spec v1.10 to RVF v2.0 (FEXT_VERSION_2_00_0), and others with Privilege spec v1.11 to RVF v2.2 (FEXT_VERSION_2_02_0). Any comments are welcome. Regards, Frank Chang > > Privilege spec v1.11 is ratified at (2019/06/10): > > https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMFDQC-and-Priv-v1.11 > > In fact, Unprivileged spec v2.2 was released at (2017/05/10): > https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-user-2.2 > > and Privilege spec v1.10 was released at (2017/05/10): > https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-priv-1.10 > > Privilege spec was then bumped to v1.11-draft in the next draft release > right after v1.10 (2018/05/24): > > https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20180524001518-9981ad7 > (RVF was still v2.0 at the time.) > > It seems that when Privilege spec v1.11 was ratified, RVF had been bumped > to v2.2, > and when Privilege spec v1.10 was ratified, RVF was still v2.0. > > As in QEMU, there's only *priv_ver* variable existing for now. > So unless we introduce other variables like: *unpriv_ver* or *fext_ver*. > Otherwise, I think using *priv_ver* is still valid here. > Though it is not accurate, somehow confused, > and may not be true anymore in future standards. > > Let me know which way is better for our maintenance. > > Thanks, > Frank Chang > > r~ >> > --0000000000009453d205ce86f021 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
On Sun, Oct 17, 2021 at 8:55 AM Frank Cha= ng <frank.chang@sifive.com= > wrote:
On Sun, Oct 17, 20= 21 at 1:56 AM Richard Henderson <richard.henderson@linaro.org> wrote:
<= /div>
On 10/16/21 1:52 AM, Frank Chang wrote:
> On Sat, Oct 16, 2021 at 1:05 AM Richard Henderson <richard.henderson@linaro.= org
> <mailto:richard.henderson@linaro.org>> wrote:
>
>=C2=A0 =C2=A0 =C2=A0On 10/14/21 11:54 PM, frank.chang@sifive.com <mailto:frank.chang@sifive.co= m> wrote:
>=C2=A0 =C2=A0 =C2=A0 > From: Chih-Min Chao<chihmin.chao@sifive.com <mail= to:chihmin.cha= o@sifive.com>>
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > The sNaN propagation behavior has been change= d since
>=C2=A0 =C2=A0 =C2=A0 > cd20cee7 inhttps://github.com/= riscv/riscv-isa-manual
>=C2=A0 =C2=A0 =C2=A0<http://github.com/riscv/riscv-is= a-manual>
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > Signed-off-by: Chih-Min Chao<chihmin.chao@sifive.com= <mailto:ch= ihmin.chao@sifive.com>>
>=C2=A0 =C2=A0 =C2=A0 > ---
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0target/riscv/fpu_helper.c | 8 +++= +----
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A01 file changed, 4 insertions(+), = 4 deletions(-)
>=C2=A0 =C2=A0 =C2=A0 >
>=C2=A0 =C2=A0 =C2=A0 > diff --git a/target/riscv/fpu_helper.c b/targ= et/riscv/fpu_helper.c
>=C2=A0 =C2=A0 =C2=A0 > index 8700516a14c..1472ead2528 100644
>=C2=A0 =C2=A0 =C2=A0 > --- a/target/riscv/fpu_helper.c
>=C2=A0 =C2=A0 =C2=A0 > +++ b/target/riscv/fpu_helper.c
>=C2=A0 =C2=A0 =C2=A0 > @@ -174,14 +174,14 @@ uint64_t helper_fmin_s(= CPURISCVState *env, uint64_t rs1,
>=C2=A0 =C2=A0 =C2=A0uint64_t rs2)
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0{
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0float32 frs1 =3D ch= eck_nanbox_s(rs1);
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0 =C2=A0 =C2=A0float32 frs2 =3D ch= eck_nanbox_s(rs2);
>=C2=A0 =C2=A0 =C2=A0 > -=C2=A0 =C2=A0 return nanbox_s(float32_minnum= (frs1, frs2, &env->fp_status));
>=C2=A0 =C2=A0 =C2=A0 > +=C2=A0 =C2=A0 return nanbox_s(float32_minnum= _noprop(frs1, frs2, &env->fp_status));
>=C2=A0 =C2=A0 =C2=A0 >=C2=A0 =C2=A0}
>
>=C2=A0 =C2=A0 =C2=A0Don't you need to conditionalize behaviour on t= he isa revision?
>
>
> I will pick the right API based on CPU privilege spec version.

There's a separate F-extension revision number: 2.2.

But I'll leave it up to those more knowledgeable about the revision com= binations actually
present in the field to decide.


I d= id some history searches on RISC-V ISA spec Github repo.

F-extension was bumped to v2.2 at (2018/08/28):
The privilege spec is v1.10-draft a= t the time.

and later ratified at (2019/03/26):
<= br>
The spec was updated to use IEEE 754-2019 min/max functions i= n commit: #cd20cee7=C2=A0(= 2019/06/05).

Sorry, the c= ommit date is 2017/06/05, not 2019/06/05.

But = I think it's probably easier and clearer to just introduce an extra = fext_ver variable.
We can set CPUs which are Privilege spec v= 1.10 to RVF v2.0 (FEXT_VERSION_2_00_0),
and others with Privilege= spec v1.11 to RVF v2.2=C2=A0(FEXT_VERSION_2_02_0).

Any comments are welcome.

Regards,
Fra= nk Chang
=C2=A0

Privi= lege spec v1.11 is ratified at (2019/06/10):
=C2=A0
In fact,= Unprivileged=C2=A0spec v2.2 was released at (2017/05/10):

and Privilege spec v1.10 was= released at (2017/05/10):

Privilege=C2=A0spec was then bumped to v1.11-draft in the = next draft release right after v1.10 (2018/05/24):
(RVF was still v2.0 at = the time.)

It seems that when Privilege spec v1.11= was ratified, RVF had been bumped to v2.2,
and when Privileg= e=C2=A0spec v1.10 was ratified, RVF was still v2.0.

As in QEMU, there's only=C2=A0priv_ver=C2=A0variable exis= ting for now.
So unless we introduce=C2=A0other=C2=A0variables li= ke:=C2=A0unpriv_ver or fext_ver.
Otherwise, I think= using priv_ver is still valid here.
Though it is no= t accurate, somehow confused,
and may not be true anymore in=C2= =A0future standards.

Let me know which way is bett= er for our maintenance.

Thanks,
Frank Ch= ang

r~
--0000000000009453d205ce86f021--