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Sun, 22 Nov 2020 17:22:25 -0800 (PST) MIME-Version: 1.0 References: <20201118083044.13992-1-frank.chang@sifive.com> <20201118083044.13992-16-frank.chang@sifive.com> <104fea2e-5c9a-8331-b9f5-4d5967651427@gmail.com> In-Reply-To: <104fea2e-5c9a-8331-b9f5-4d5967651427@gmail.com> From: Frank Chang Date: Mon, 23 Nov 2020 09:22:15 +0800 Message-ID: Subject: Re: [RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line To: Alistair Francis Content-Type: multipart/alternative; boundary="000000000000dd293d05b4bc0619" Received-SPF: pass client-ip=2607:f8b0:4864:20::341; envelope-from=frank.chang@sifive.com; helo=mail-ot1-x341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Sagar Karandikar , Bastian Koppelmann , "qemu-devel@nongnu.org Developers" , Palmer Dabbelt , Alistair Francis , Kito Cheng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000dd293d05b4bc0619 Content-Type: text/plain; charset="UTF-8" On Sat, Nov 21, 2020 at 12:24 AM Alistair Francis wrote: > > > On 19/11/2020 7:02 pm, Kito Cheng wrote: > >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > >> index 0bbfd7f4574..bc29e118c6d 100644 > >> --- a/target/riscv/cpu.c > >> +++ b/target/riscv/cpu.c > >> @@ -438,6 +438,9 @@ static void riscv_cpu_realize(DeviceState *dev, > Error **errp) > >> if (cpu->cfg.ext_h) { > >> target_misa |= RVH; > >> } > >> + if (cpu->cfg.ext_b) { > >> + target_misa |= RVB; > >> + } > >> if (cpu->cfg.ext_v) { > >> target_misa |= RVV; > >> if (!is_power_of_2(cpu->cfg.vlen)) { > >> @@ -515,6 +518,7 @@ static Property riscv_cpu_properties[] = { > >> DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), > >> DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), > >> /* This is experimental so mark with 'x-' */ > >> + DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, true), > > > > I think the default value should be false? > > Good catch, I missed that. > > Yes it should be false. > > Alistair > Thanks, I'll fix it in my next patchset. Frank Chang > > > > >> DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), > >> DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), > >> DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), > > > --000000000000dd293d05b4bc0619 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
On Sat, Nov 21, 2020 at 12:24 AM Alistair= Francis <alistair23@gmail.com> wrote:


On 19/11/2020 7:02 pm, Kito Cheng wrote:
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 0bbfd7f4574..bc29e118c6d 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -438,6 +438,9 @@ static void riscv_cpu_realize(DeviceState *dev= , Error **errp)
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (cpu->cfg.ext_h) { >>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_misa = |=3D RVH;
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (cpu->cfg.ext_b) {
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 target_misa |=3D RVB; >> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (cpu->cfg.ext_v) { >>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_misa = |=3D RVV;
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (!is_powe= r_of_2(cpu->cfg.vlen)) {
>> @@ -515,6 +518,7 @@ static Property riscv_cpu_properties[] =3D { >>=C2=A0 =C2=A0 =C2=A0 =C2=A0DEFINE_PROP_BOOL("s", RISCVCPU= , cfg.ext_s, true),
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0DEFINE_PROP_BOOL("u", RISCVCPU= , cfg.ext_u, true),
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0/* This is experimental so mark with = 9;x-' */
>> +=C2=A0 =C2=A0 DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext= _b, true),
>
> I think the default value should be false?

Good catch, I missed that.

Yes it should be false.

Alistair


<= blockquote class=3D"gmail_quote" style=3D"margin:0px 0px 0px 0.8ex;border-l= eft:1px solid rgb(204,204,204);padding-left:1ex">
>
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0DEFINE_PROP_BOOL("x-h", RISCVC= PU, cfg.ext_h, false),
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0DEFINE_PROP_BOOL("x-v", RISCVC= PU, cfg.ext_v, false),
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0DEFINE_PROP_BOOL("Counters", R= ISCVCPU, cfg.ext_counters, true),
>
--000000000000dd293d05b4bc0619--