From: Frank Chang <frank.chang@sifive.com>
To: Alexandre Ghiti <alexghiti@rivosinc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Andrew Jones <ajones@ventanamicro.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Bin Meng <bmeng@tinylab.org>
Subject: Re: [PATCH v10 4/5] riscv: Introduce satp mode hw capabilities
Date: Fri, 3 Feb 2023 15:58:06 +0800 [thread overview]
Message-ID: <CAE_xrPgJLZkhxL6HCiY2ZAoAVGgihgOaY9cuy7LA3_ocTWEH4w@mail.gmail.com> (raw)
In-Reply-To: <20230203055812.257458-5-alexghiti@rivosinc.com>
[-- Attachment #1: Type: text/plain, Size: 10606 bytes --]
Reviewed-by: Frank Chang <frank.chang@sifive.com>
On Fri, Feb 3, 2023 at 2:02 PM Alexandre Ghiti <alexghiti@rivosinc.com>
wrote:
> Currently, the max satp mode is set with the only constraint that it must
> be
> implemented in QEMU, i.e. set in valid_vm_1_10_[32|64].
>
> But we actually need to add another level of constraint: what the hw is
> actually capable of, because currently, a linux booting on a sifive-u54
> boots in sv57 mode which is incompatible with the cpu's sv39 max
> capability.
>
> So add a new bitmap to RISCVSATPMap which contains this capability and
> initialize it in every XXX_cpu_init.
>
> Finally:
> - valid_vm_1_10_[32|64] constrains which satp mode the CPU can use
> - the CPU hw capabilities constrains what the user may select
> - the user's selection then constrains what's available to the guest
> OS.
>
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: Bin Meng <bmeng@tinylab.org>
> ---
> target/riscv/cpu.c | 91 +++++++++++++++++++++++++++++++++-------------
> target/riscv/cpu.h | 8 +++-
> 2 files changed, 72 insertions(+), 27 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 56057cf87c..7e9924ede9 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -293,18 +293,24 @@ const char *satp_mode_str(uint8_t satp_mode, bool
> is_32_bit)
> g_assert_not_reached();
> }
>
> -/* Sets the satp mode to the max supported */
> -static void set_satp_mode_default_map(RISCVCPU *cpu)
> +static void set_satp_mode_max_supported(RISCVCPU *cpu,
> + uint8_t satp_mode)
> {
> bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
> + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
>
> - if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) {
> - cpu->cfg.satp_mode.map |=
> - (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57"));
> - } else {
> - cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare"));
> + for (int i = 0; i <= satp_mode; ++i) {
> + if (valid_vm[i]) {
> + cpu->cfg.satp_mode.supported |= (1 << i);
> + }
> }
> }
> +
> +/* Set the satp mode to the max supported */
> +static void set_satp_mode_default_map(RISCVCPU *cpu)
> +{
> + cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported;
> +}
> #endif
>
> static void riscv_any_cpu_init(Object *obj)
> @@ -315,6 +321,13 @@ static void riscv_any_cpu_init(Object *obj)
> #elif defined(TARGET_RISCV64)
> set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
> #endif
> +
> +#ifndef CONFIG_USER_ONLY
> + set_satp_mode_max_supported(RISCV_CPU(obj),
> + riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
> + VM_1_10_SV32 : VM_1_10_SV57);
> +#endif
> +
> set_priv_version(env, PRIV_VERSION_1_12_0);
> register_cpu_props(obj);
> }
> @@ -328,6 +341,9 @@ static void rv64_base_cpu_init(Object *obj)
> register_cpu_props(obj);
> /* Set latest version of privileged specification */
> set_priv_version(env, PRIV_VERSION_1_12_0);
> +#ifndef CONFIG_USER_ONLY
> + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
> +#endif
> }
>
> static void rv64_sifive_u_cpu_init(Object *obj)
> @@ -335,6 +351,9 @@ static void rv64_sifive_u_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS |
> RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> +#ifndef CONFIG_USER_ONLY
> + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
> +#endif
> }
>
> static void rv64_sifive_e_cpu_init(Object *obj)
> @@ -345,6 +364,9 @@ static void rv64_sifive_e_cpu_init(Object *obj)
> set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> cpu->cfg.mmu = false;
> +#ifndef CONFIG_USER_ONLY
> + set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> +#endif
> }
>
> static void rv128_base_cpu_init(Object *obj)
> @@ -361,6 +383,9 @@ static void rv128_base_cpu_init(Object *obj)
> register_cpu_props(obj);
> /* Set latest version of privileged specification */
> set_priv_version(env, PRIV_VERSION_1_12_0);
> +#ifndef CONFIG_USER_ONLY
> + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
> +#endif
> }
> #else
> static void rv32_base_cpu_init(Object *obj)
> @@ -371,6 +396,9 @@ static void rv32_base_cpu_init(Object *obj)
> register_cpu_props(obj);
> /* Set latest version of privileged specification */
> set_priv_version(env, PRIV_VERSION_1_12_0);
> +#ifndef CONFIG_USER_ONLY
> + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
> +#endif
> }
>
> static void rv32_sifive_u_cpu_init(Object *obj)
> @@ -378,6 +406,9 @@ static void rv32_sifive_u_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS |
> RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> +#ifndef CONFIG_USER_ONLY
> + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
> +#endif
> }
>
> static void rv32_sifive_e_cpu_init(Object *obj)
> @@ -388,6 +419,9 @@ static void rv32_sifive_e_cpu_init(Object *obj)
> set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> cpu->cfg.mmu = false;
> +#ifndef CONFIG_USER_ONLY
> + set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> +#endif
> }
>
> static void rv32_ibex_cpu_init(Object *obj)
> @@ -398,6 +432,9 @@ static void rv32_ibex_cpu_init(Object *obj)
> set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_11_0);
> cpu->cfg.mmu = false;
> +#ifndef CONFIG_USER_ONLY
> + set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> +#endif
> cpu->cfg.epmp = true;
> }
>
> @@ -409,6 +446,9 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
> set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> cpu->cfg.mmu = false;
> +#ifndef CONFIG_USER_ONLY
> + set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> +#endif
> }
> #endif
>
> @@ -701,8 +741,9 @@ static void riscv_cpu_disas_set_info(CPUState *s,
> disassemble_info *info)
> static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
> {
> bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
> - const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
> - uint8_t satp_mode_max;
> + uint8_t satp_mode_map_max;
> + uint8_t satp_mode_supported_max =
> +
> satp_mode_max_from_map(cpu->cfg.satp_mode.supported);
>
> if (cpu->cfg.satp_mode.map == 0) {
> if (cpu->cfg.satp_mode.init == 0) {
> @@ -715,9 +756,10 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU
> *cpu, Error **errp)
> * valid_vm_1_10_32/64.
> */
> for (int i = 1; i < 16; ++i) {
> - if ((cpu->cfg.satp_mode.init & (1 << i)) && valid_vm[i]) {
> + if ((cpu->cfg.satp_mode.init & (1 << i)) &&
> + (cpu->cfg.satp_mode.supported & (1 << i))) {
> for (int j = i - 1; j >= 0; --j) {
> - if (valid_vm[j]) {
> + if (cpu->cfg.satp_mode.supported & (1 << j)) {
> cpu->cfg.satp_mode.map |= (1 << j);
> break;
> }
> @@ -728,37 +770,36 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU
> *cpu, Error **errp)
> }
> }
>
> - /* Make sure the configuration asked is supported by qemu */
> - for (int i = 0; i < 16; ++i) {
> - if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) {
> - error_setg(errp, "satp_mode %s is not valid",
> - satp_mode_str(i, rv32));
> - return;
> - }
> + satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
> +
> + /* Make sure the user asked for a supported configuration (HW and
> qemu) */
> + if (satp_mode_map_max > satp_mode_supported_max) {
> + error_setg(errp, "satp_mode %s is higher than hw max capability
> %s",
> + satp_mode_str(satp_mode_map_max, rv32),
> + satp_mode_str(satp_mode_supported_max, rv32));
> + return;
> }
>
> /*
> * Make sure the user did not ask for an invalid configuration as per
> * the specification.
> */
> - satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
> -
> if (!rv32) {
> - for (int i = satp_mode_max - 1; i >= 0; --i) {
> + for (int i = satp_mode_map_max - 1; i >= 0; --i) {
> if (!(cpu->cfg.satp_mode.map & (1 << i)) &&
> (cpu->cfg.satp_mode.init & (1 << i)) &&
> - valid_vm[i]) {
> + (cpu->cfg.satp_mode.supported & (1 << i))) {
> error_setg(errp, "cannot disable %s satp mode if %s "
> "is enabled", satp_mode_str(i, false),
> - satp_mode_str(satp_mode_max, false));
> + satp_mode_str(satp_mode_map_max, false));
> return;
> }
> }
> }
>
> /* Finally expand the map so that all valid modes are set */
> - for (int i = satp_mode_max - 1; i >= 0; --i) {
> - if (valid_vm[i]) {
> + for (int i = satp_mode_map_max - 1; i >= 0; --i) {
> + if (cpu->cfg.satp_mode.supported & (1 << i)) {
> cpu->cfg.satp_mode.map |= (1 << i);
> }
> }
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index df6d9e06e4..defc5769b5 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -416,13 +416,17 @@ struct RISCVCPUClass {
>
> /*
> * map is a 16-bit bitmap: the most significant set bit in map is the
> maximum
> - * satp mode that is supported.
> + * satp mode that is supported. It may be chosen by the user and must
> respect
> + * what qemu implements (valid_1_10_32/64) and what the hw is capable of
> + * (supported bitmap below).
> *
> * init is a 16-bit bitmap used to make sure the user selected a correct
> * configuration as per the specification.
> + *
> + * supported is a 16-bit bitmap used to reflect the hw capabilities.
> */
> typedef struct {
> - uint16_t map, init;
> + uint16_t map, init, supported;
> } RISCVSATPMap;
>
> struct RISCVCPUConfig {
> --
> 2.37.2
>
>
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next prev parent reply other threads:[~2023-02-03 8:00 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-03 5:58 [PATCH v10 0/5] riscv: Allow user to set the satp mode Alexandre Ghiti
2023-02-03 5:58 ` [PATCH v10 1/5] riscv: Pass Object to register_cpu_props instead of DeviceState Alexandre Ghiti
2023-02-03 5:58 ` [PATCH v10 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool Alexandre Ghiti
2023-02-03 5:58 ` [PATCH v10 3/5] riscv: Allow user to set the satp mode Alexandre Ghiti
2023-02-03 8:01 ` Frank Chang
2023-02-03 5:58 ` [PATCH v10 4/5] riscv: Introduce satp mode hw capabilities Alexandre Ghiti
2023-02-03 7:58 ` Frank Chang [this message]
2023-02-05 23:11 ` Alistair Francis
2023-02-03 5:58 ` [PATCH v10 5/5] riscv: Correctly set the device-tree entry 'mmu-type' Alexandre Ghiti
2023-03-02 17:42 ` [PATCH v10 0/5] riscv: Allow user to set the satp mode Daniel Henrique Barboza
2023-03-02 21:03 ` Daniel Henrique Barboza
2023-03-03 11:52 ` Alexandre Ghiti
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