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Mon, 18 Apr 2022 23:00:45 -0700 (PDT) MIME-Version: 1.0 References: <20220415093727.15323-1-frank.chang@sifive.com> In-Reply-To: From: Frank Chang Date: Tue, 19 Apr 2022 14:00:34 +0800 Message-ID: Subject: Re: [PATCH] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values To: Anup Patel Content-Type: multipart/alternative; boundary="000000000000fd9de205dcfb98f5" Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=frank.chang@sifive.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , "open list:RISC-V" , Bin Meng , "qemu-devel@nongnu.org Developers" , Jim Shu , Palmer Dabbelt , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000fd9de205dcfb98f5 Content-Type: text/plain; charset="UTF-8" On Tue, Apr 19, 2022 at 1:27 PM Anup Patel wrote: > On Tue, Apr 19, 2022 at 10:52 AM Alistair Francis > wrote: > > > > On Fri, Apr 15, 2022 at 7:37 PM wrote: > > > > > > From: Frank Chang > > > > > > Allow user to set core's marchid, mvendorid, mipid CSRs through > > > -cpu command line option. > > > > > > Signed-off-by: Frank Chang > > > Reviewed-by: Jim Shu > > > --- > > > target/riscv/cpu.c | 4 ++++ > > > target/riscv/cpu.h | 4 ++++ > > > target/riscv/csr.c | 38 ++++++++++++++++++++++++++++++++++---- > > > 3 files changed, 42 insertions(+), 4 deletions(-) > > > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > > index ddda4906ff..2eea0f9be7 100644 > > > --- a/target/riscv/cpu.c > > > +++ b/target/riscv/cpu.c > > > @@ -786,6 +786,10 @@ static Property riscv_cpu_properties[] = { > > > DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), > > > DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), > > > > > > + DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), > > > + DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, 0), > > > + DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, 0), > > > > Should we have non-zero defaults here? > > To do that, we need mvendorid for QEMU RISC-V. > > The marchid and mipid can be based on the QEMU version number. > > Regards, > Anup > The original intention for this patch is to allow users to define their own $mvendorid, $marchid, and $mipid through the command line when they initiate QEMU. If we want to provide the default values for QEMU RISC-V CPU, just like what Anup said. We need to define our own mvendorid, which should be a JEDEC manufacturer ID. (Perhaps it's fine to just give some random legal JEDEC manufacturer ID as I don't think we would really want to spend the money on that.) For $marchid and $mipid, I agree that it could base on QEMU's version from the QEMU_FULL_VERSION macro. (and $marchid should have MSB set to 1 for open-source projects.) Regards, Frank Chang > > > > > Alistair > > > > > + > > > DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), > > > DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), > > > DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > > index c069fe85fa..3ab92deb4b 100644 > > > --- a/target/riscv/cpu.h > > > +++ b/target/riscv/cpu.h > > > @@ -370,6 +370,10 @@ struct RISCVCPUConfig { > > > bool ext_zve32f; > > > bool ext_zve64f; > > > > > > + uint32_t mvendorid; > > > + uint64_t marchid; > > > + uint64_t mipid; > > > + > > > /* Vendor-specific custom extensions */ > > > bool ext_XVentanaCondOps; > > > > > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > > index 341c2e6f23..9a02038adb 100644 > > > --- a/target/riscv/csr.c > > > +++ b/target/riscv/csr.c > > > @@ -603,6 +603,36 @@ static RISCVException write_ignore(CPURISCVState > *env, int csrno, > > > return RISCV_EXCP_NONE; > > > } > > > > > > +static RISCVException read_mvendorid(CPURISCVState *env, int csrno, > > > + target_ulong *val) > > > +{ > > > + CPUState *cs = env_cpu(env); > > > + RISCVCPU *cpu = RISCV_CPU(cs); > > > + > > > + *val = cpu->cfg.mvendorid; > > > + return RISCV_EXCP_NONE; > > > +} > > > + > > > +static RISCVException read_marchid(CPURISCVState *env, int csrno, > > > + target_ulong *val) > > > +{ > > > + CPUState *cs = env_cpu(env); > > > + RISCVCPU *cpu = RISCV_CPU(cs); > > > + > > > + *val = cpu->cfg.marchid; > > > + return RISCV_EXCP_NONE; > > > +} > > > + > > > +static RISCVException read_mipid(CPURISCVState *env, int csrno, > > > + target_ulong *val) > > > +{ > > > + CPUState *cs = env_cpu(env); > > > + RISCVCPU *cpu = RISCV_CPU(cs); > > > + > > > + *val = cpu->cfg.mipid; > > > + return RISCV_EXCP_NONE; > > > +} > > > + > > > static RISCVException read_mhartid(CPURISCVState *env, int csrno, > > > target_ulong *val) > > > { > > > @@ -3098,10 +3128,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = > { > > > [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, > > > > > > /* Machine Information Registers */ > > > - [CSR_MVENDORID] = { "mvendorid", any, read_zero }, > > > - [CSR_MARCHID] = { "marchid", any, read_zero }, > > > - [CSR_MIMPID] = { "mimpid", any, read_zero }, > > > - [CSR_MHARTID] = { "mhartid", any, read_mhartid }, > > > + [CSR_MVENDORID] = { "mvendorid", any, read_mvendorid }, > > > + [CSR_MARCHID] = { "marchid", any, read_marchid }, > > > + [CSR_MIMPID] = { "mimpid", any, read_mipid }, > > > + [CSR_MHARTID] = { "mhartid", any, read_mhartid }, > > > > > > /* Machine Trap Setup */ > > > [CSR_MSTATUS] = { "mstatus", any, read_mstatus, > write_mstatus, NULL, > > > -- > > > 2.35.1 > > > > > > > > > --000000000000fd9de205dcfb98f5 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
On Tue, Apr 19, 2022 at 1:27 PM Anup Pate= l <apatel@ventanamicro.com> wrote:
On Tue, Apr 19, 2022 at 10:52 AM Alistair Francis &= lt;alistair23@gma= il.com> wrote:
>
> On Fri, Apr 15, 2022 at 7:37 PM <frank.chang@sifive.com> wrote:
> >
> > From: Frank Chang <frank.chang@sifive.com>
> >
> > Allow user to set core's marchid, mvendorid, mipid CSRs throu= gh
> > -cpu command line option.
> >
> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
> > Reviewed-by: Jim Shu <jim.shu@sifive.com>
> > ---
> >=C2=A0 target/riscv/cpu.c |=C2=A0 4 ++++
> >=C2=A0 target/riscv/cpu.h |=C2=A0 4 ++++
> >=C2=A0 target/riscv/csr.c | 38 ++++++++++++++++++++++++++++++++++-= ---
> >=C2=A0 3 files changed, 42 insertions(+), 4 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index ddda4906ff..2eea0f9be7 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -786,6 +786,10 @@ static Property riscv_cpu_properties[] =3D {=
> >=C2=A0 =C2=A0 =C2=A0 DEFINE_PROP_UINT16("vlen", RISCVCPU= , cfg.vlen, 128),
> >=C2=A0 =C2=A0 =C2=A0 DEFINE_PROP_UINT16("elen", RISCVCPU= , cfg.elen, 64),
> >
> > +=C2=A0 =C2=A0 DEFINE_PROP_UINT32("mvendorid", RISCVCPU= , cfg.mvendorid, 0),
> > +=C2=A0 =C2=A0 DEFINE_PROP_UINT64("marchid", RISCVCPU, = cfg.marchid, 0),
> > +=C2=A0 =C2=A0 DEFINE_PROP_UINT64("mipid", RISCVCPU, cf= g.mipid, 0),
>
> Should we have non-zero defaults here?

To do that, we need mvendorid for QEMU RISC-V.

The marchid and mipid can be based on the QEMU version number.

Regards,
Anup

The original intention for this pa= tch is to allow users to define
their own $mvendorid, $marchid, a= nd $mipid through the command line
when they initiate QEMU.
=

If we want to provide the default values for QEMU RISC-= V CPU,
just like what Anup said.
We need to define our = own mvendorid, which should be a JEDEC manufacturer ID.
(Perhaps = it's fine to just give some random legal JEDEC manufacturer ID
as I don't think we would really want to spend the money on that.)

For $marchid and $mipid,
I agree that it c= ould=C2=A0base on QEMU's version from the QEMU_FULL_VERSION macro.
(and $marchid should have MSB set to 1 for open-source projects.)

Regards,
Frank Chang
=C2=A0

>
> Alistair
>
> > +
> >=C2=A0 =C2=A0 =C2=A0 DEFINE_PROP_BOOL("svinval", RISCVCP= U, cfg.ext_svinval, false),
> >=C2=A0 =C2=A0 =C2=A0 DEFINE_PROP_BOOL("svnapot", RISCVCP= U, cfg.ext_svnapot, false),
> >=C2=A0 =C2=A0 =C2=A0 DEFINE_PROP_BOOL("svpbmt", RISCVCPU= , cfg.ext_svpbmt, false),
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index c069fe85fa..3ab92deb4b 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -370,6 +370,10 @@ struct RISCVCPUConfig {
> >=C2=A0 =C2=A0 =C2=A0 bool ext_zve32f;
> >=C2=A0 =C2=A0 =C2=A0 bool ext_zve64f;
> >
> > +=C2=A0 =C2=A0 uint32_t mvendorid;
> > +=C2=A0 =C2=A0 uint64_t marchid;
> > +=C2=A0 =C2=A0 uint64_t mipid;
> > +
> >=C2=A0 =C2=A0 =C2=A0 /* Vendor-specific custom extensions */
> >=C2=A0 =C2=A0 =C2=A0 bool ext_XVentanaCondOps;
> >
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index 341c2e6f23..9a02038adb 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -603,6 +603,36 @@ static RISCVException write_ignore(CPURISCVS= tate *env, int csrno,
> >=C2=A0 =C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> >=C2=A0 }
> >
> > +static RISCVException read_mvendorid(CPURISCVState *env, int csr= no,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target= _ulong *val)
> > +{
> > +=C2=A0 =C2=A0 CPUState *cs =3D env_cpu(env);
> > +=C2=A0 =C2=A0 RISCVCPU *cpu =3D RISCV_CPU(cs);
> > +
> > +=C2=A0 =C2=A0 *val =3D cpu->cfg.mvendorid;
> > +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> > +}
> > +
> > +static RISCVException read_marchid(CPURISCVState *env, int csrno= ,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong = *val)
> > +{
> > +=C2=A0 =C2=A0 CPUState *cs =3D env_cpu(env);
> > +=C2=A0 =C2=A0 RISCVCPU *cpu =3D RISCV_CPU(cs);
> > +
> > +=C2=A0 =C2=A0 *val =3D cpu->cfg.marchid;
> > +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> > +}
> > +
> > +static RISCVException read_mipid(CPURISCVState *env, int csrno,<= br> > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong *val) > > +{
> > +=C2=A0 =C2=A0 CPUState *cs =3D env_cpu(env);
> > +=C2=A0 =C2=A0 RISCVCPU *cpu =3D RISCV_CPU(cs);
> > +
> > +=C2=A0 =C2=A0 *val =3D cpu->cfg.mipid;
> > +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> > +}
> > +
> >=C2=A0 static RISCVException read_mhartid(CPURISCVState *env, int = csrno,
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_ul= ong *val)
> >=C2=A0 {
> > @@ -3098,10 +3128,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SI= ZE] =3D {
> >=C2=A0 =C2=A0 =C2=A0 [CSR_MINSTRETH] =3D { "minstreth", = any32, read_instreth },
> >
> >=C2=A0 =C2=A0 =C2=A0 /* Machine Information Registers */
> > -=C2=A0 =C2=A0 [CSR_MVENDORID] =3D { "mvendorid", any,= =C2=A0 =C2=A0read_zero=C2=A0 =C2=A0 },
> > -=C2=A0 =C2=A0 [CSR_MARCHID]=C2=A0 =C2=A0=3D { "marchid"= ;,=C2=A0 =C2=A0any,=C2=A0 =C2=A0read_zero=C2=A0 =C2=A0 },
> > -=C2=A0 =C2=A0 [CSR_MIMPID]=C2=A0 =C2=A0 =3D { "mimpid"= ,=C2=A0 =C2=A0 any,=C2=A0 =C2=A0read_zero=C2=A0 =C2=A0 },
> > -=C2=A0 =C2=A0 [CSR_MHARTID]=C2=A0 =C2=A0=3D { "mhartid"= ;,=C2=A0 =C2=A0any,=C2=A0 =C2=A0read_mhartid },
> > +=C2=A0 =C2=A0 [CSR_MVENDORID] =3D { "mvendorid", any,= =C2=A0 =C2=A0read_mvendorid },
> > +=C2=A0 =C2=A0 [CSR_MARCHID]=C2=A0 =C2=A0=3D { "marchid"= ;,=C2=A0 =C2=A0any,=C2=A0 =C2=A0read_marchid=C2=A0 =C2=A0},
> > +=C2=A0 =C2=A0 [CSR_MIMPID]=C2=A0 =C2=A0 =3D { "mimpid"= ,=C2=A0 =C2=A0 any,=C2=A0 =C2=A0read_mipid=C2=A0 =C2=A0 =C2=A0},
> > +=C2=A0 =C2=A0 [CSR_MHARTID]=C2=A0 =C2=A0=3D { "mhartid"= ;,=C2=A0 =C2=A0any,=C2=A0 =C2=A0read_mhartid=C2=A0 =C2=A0},
> >
> >=C2=A0 =C2=A0 =C2=A0 /* Machine Trap Setup */
> >=C2=A0 =C2=A0 =C2=A0 [CSR_MSTATUS]=C2=A0 =C2=A0 =C2=A0=3D { "= mstatus",=C2=A0 =C2=A0 any,=C2=A0 =C2=A0read_mstatus,=C2=A0 =C2=A0 =C2= =A0write_mstatus, NULL,
> > --
> > 2.35.1
> >
> >
>
--000000000000fd9de205dcfb98f5--