From: Frank Chang <frank.chang@sifive.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
Date: Tue, 14 Jul 2020 12:39:24 +0800 [thread overview]
Message-ID: <CAE_xrPiNfu2f0fMfVes6PF-HPRuP7-dFuVEidMYFGLfwGhdcEA@mail.gmail.com> (raw)
In-Reply-To: <407ef5d5-d9d9-9619-b6e3-456f8a5b4bfb@c-sky.com>
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On Tue, Jul 14, 2020 at 11:35 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
>
> On 2020/7/14 10:59, Frank Chang wrote:
>
> On Sat, Jul 11, 2020 at 12:27 AM Richard Henderson <
> richard.henderson@linaro.org> wrote:
>
>> On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
>> > From: Frank Chang <frank.chang@sifive.com>
>> >
>> > vsll.vi, vsrl.vi, vsra.vi cannot use shli gvec as it requires the
>> > shift immediate value to be within the range: [0.. SEW bits].
>> > Otherwise, it will hit the assertion:
>> > tcg_debug_assert(shift >= 0 && shift < (8 << vece));
>> >
>> > However, RVV spec does not have such constraint, therefore we have to
>> > use helper functions instead.
>>
>> Why do you say that? It does have such a constraint:
>>
>> # Only the low lg2(SEW) bits are read to obtain the shift amount from a
>> register value.
>>
>> While that only talks about the register value, I sincerely doubt that
>> the same
>> truncation does not actually apply to immediates.
>>
>> And if the entire immediate value does apply, the manual should certainly
>> specify what should happen in that case. And at present it doesn't.
>>
>> It seems to me the bug is the bare use of GEN_OPIVI_GVEC_TRANS and thence
>> do_opivi_gvec. The ZX parameter should be extended to more than just
>> "zero vs
>> sign-extend", it should have an option for truncating the immediate to
>> s->sew.
>>
>>
>> r~
>>
>
> The latest spec specified:
>
> Only the low *lg2(SEW) bits* are read to obtain the shift amount from a *register
> value*.
> The *immediate* is treated as an *unsigned shift amount*, with a *maximum
> shift amount of 31*.
>
> Looks like the shift amount in the immediate value is not relevant with
> SEW setting.
> If so, is it better to just use do_opivi_gvec() and implement the logic by
> our own rather than using gvec IR?
>
>
> In my opinion, it doesn't matter to truncate the immediate to s->sew
> before calling the gvec IR,
> whether the constraint of immediate exits or not.
>
> Zhiwei
>
>
> Frank Chang
>
>
>
The current issue I've encountered is the test like:
*vsetvli t0,t0,e8,m1,tu,mu,d1*
*vsll.vi <http://vsll.vi> v30, v30, 27*
where the SEW is 8 (i.e. vece = 0), but the immediate value is: 27.
The instruction doesn't violate the requirement specified in spec as its
value is less then 31.
However, it can't pass *tcg_debug_assert(shift >= 0 && shift < (8 <<
vece));* assertion if tcg debug option is enabled.
Frank Chang
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next prev parent reply other threads:[~2020-07-14 4:40 UTC|newest]
Thread overview: 107+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-10 10:48 [RFC 00/65] target/riscv: support vector extension v0.9 frank.chang
2020-07-10 10:48 ` [RFC 01/65] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion frank.chang
2020-07-10 16:12 ` Richard Henderson
2020-07-10 18:24 ` Alistair Francis
2020-07-10 10:48 ` [RFC 02/65] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() frank.chang
2020-07-10 16:13 ` Richard Henderson
2020-07-10 10:48 ` [RFC 03/65] target/riscv: fix return value of do_opivx_widen() frank.chang
2020-07-10 16:14 ` Richard Henderson
2020-07-10 10:48 ` [RFC 04/65] target/riscv: fix vill bit index in vtype register frank.chang
2020-07-10 16:15 ` Richard Henderson
2020-07-10 10:48 ` [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec frank.chang
2020-07-10 16:27 ` Richard Henderson
2020-07-14 2:59 ` Frank Chang
2020-07-14 3:35 ` LIU Zhiwei
2020-07-14 4:39 ` Frank Chang [this message]
2020-07-14 13:21 ` Richard Henderson
2020-07-14 13:59 ` Frank Chang
2020-07-15 2:52 ` LIU Zhiwei
2020-07-10 10:48 ` [RFC 06/65] target/riscv: rvv-0.9: add vcsr register frank.chang
2020-07-10 17:02 ` Richard Henderson
2020-07-10 10:48 ` [RFC 07/65] target/riscv: rvv-0.9: add vector context status frank.chang
2020-07-10 17:26 ` Richard Henderson
2020-07-10 17:27 ` Richard Henderson
2020-07-10 10:48 ` [RFC 08/65] target/riscv: rvv-0.9: update mstatus_vs by tb_flags frank.chang
2020-07-10 17:28 ` Richard Henderson
2020-07-10 10:48 ` [RFC 09/65] target/riscv: rvv-0.9: add vlenb register frank.chang
2020-07-10 17:31 ` Richard Henderson
2020-07-10 10:48 ` [RFC 10/65] target/riscv: rvv-0.9: remove MLEN calculations frank.chang
2020-07-10 17:32 ` Richard Henderson
2020-07-10 10:48 ` [RFC 11/65] target/riscv: rvv-0.9: add fractional LMUL, VTA and VMA frank.chang
2020-07-10 17:45 ` Richard Henderson
2020-07-10 10:48 ` [RFC 12/65] target/riscv: rvv-0.9: update check functions frank.chang
2020-07-10 17:51 ` Richard Henderson
2020-07-13 2:10 ` Frank Chang
2020-07-10 10:48 ` [RFC 13/65] target/riscv: rvv-0.9: configure instructions frank.chang
2020-07-10 18:06 ` Richard Henderson
2020-07-13 2:07 ` Frank Chang
2020-07-10 10:48 ` [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions frank.chang
2020-07-10 18:15 ` Richard Henderson
2020-07-13 2:04 ` Frank Chang
2020-07-10 10:48 ` [RFC 15/65] target/riscv: rvv-0.9: index " frank.chang
2020-07-10 10:48 ` [RFC 16/65] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns frank.chang
2020-07-10 10:48 ` [RFC 17/65] target/riscv: rvv-0.9: fault-only-first unit stride load frank.chang
2020-07-10 10:48 ` [RFC 18/65] target/riscv: rvv-0.9: amo operations frank.chang
2020-07-10 10:48 ` [RFC 19/65] target/riscv: rvv-0.9: load/store whole register instructions frank.chang
2020-07-10 10:48 ` [RFC 20/65] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns frank.chang
2020-07-10 10:48 ` [RFC 21/65] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation frank.chang
2020-07-10 10:48 ` [RFC 22/65] target/riscv: rvv-0.9: floating-point square-root instruction frank.chang
2020-07-10 10:48 ` [RFC 23/65] target/riscv: rvv-0.9: floating-point classify instructions frank.chang
2020-07-10 10:48 ` [RFC 24/65] target/riscv: rvv-0.9: mask population count instruction frank.chang
2020-07-10 10:48 ` [RFC 25/65] target/riscv: rvv-0.9: find-first-set mask bit instruction frank.chang
2020-07-10 10:48 ` [RFC 26/65] target/riscv: rvv-0.9: set-X-first mask bit instructions frank.chang
2020-07-10 10:48 ` [RFC 27/65] target/riscv: rvv-0.9: iota instruction frank.chang
2020-07-10 10:48 ` [RFC 28/65] target/riscv: rvv-0.9: element index instruction frank.chang
2020-07-10 10:48 ` [RFC 29/65] target/riscv: rvv-0.9: integer scalar move instructions frank.chang
2020-07-10 10:48 ` [RFC 30/65] target/riscv: rvv-0.9: floating-point " frank.chang
2020-07-10 10:48 ` [RFC 31/65] target/riscv: rvv-0.9: whole register " frank.chang
2020-07-10 10:48 ` [RFC 32/65] target/riscv: rvv-0.9: integer extension instructions frank.chang
2020-07-10 10:48 ` [RFC 33/65] target/riscv: rvv-0.9: single-width averaging add and subtract instructions frank.chang
2020-07-10 10:48 ` [RFC 34/65] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow frank.chang
2020-07-10 10:48 ` [RFC 35/65] target/riscv: rvv-0.9: narrowing integer right shift instructions frank.chang
2020-07-10 10:48 ` [RFC 36/65] target/riscv: rvv-0.9: widening integer multiply-add instructions frank.chang
2020-07-10 10:48 ` [RFC 37/65] target/riscv: rvv-0.9: quad-widening " frank.chang
2020-07-10 10:48 ` [RFC 38/65] target/riscv: rvv-0.9: integer merge and move instructions frank.chang
2020-07-10 10:48 ` [RFC 39/65] target/riscv: rvv-0.9: single-width saturating add and subtract instructions frank.chang
2020-07-10 10:48 ` [RFC 40/65] target/riscv: rvv-0.9: integer comparison instructions frank.chang
2020-07-10 10:48 ` [RFC 41/65] target/riscv: rvv-0.9: floating-point compare instructions frank.chang
2020-07-10 10:48 ` [RFC 42/65] target/riscv: rvv-0.9: single-width integer reduction instructions frank.chang
2020-07-10 10:48 ` [RFC 43/65] target/riscv: rvv-0.9: widening " frank.chang
2020-07-10 10:48 ` [RFC 44/65] target/riscv: rvv-0.9: mask-register logical instructions frank.chang
2020-07-10 10:48 ` [RFC 45/65] target/riscv: rvv-0.9: register gather instructions frank.chang
2020-07-10 10:49 ` [RFC 46/65] target/riscv: rvv-0.9: slide instructions frank.chang
2020-07-10 10:49 ` [RFC 47/65] target/riscv: rvv-0.9: floating-point " frank.chang
2020-07-10 10:49 ` [RFC 48/65] target/riscv: rvv-0.9: narrowing fixed-point clip instructions frank.chang
2020-07-10 10:49 ` [RFC 49/65] target/riscv: rvv-0.9: floating-point move instructions frank.chang
2020-07-10 10:49 ` [RFC 50/65] target/riscv: rvv-0.9: floating-point/integer type-convert instructions frank.chang
2020-07-10 10:49 ` [RFC 51/65] target/riscv: rvv-0.9: single-width floating-point reduction frank.chang
2020-07-10 10:49 ` [RFC 52/65] target/riscv: rvv-0.9: widening floating-point reduction instructions frank.chang
2020-07-10 10:49 ` [RFC 53/65] target/riscv: rvv-0.9: single-width scaling shift instructions frank.chang
2020-07-10 10:49 ` [RFC 54/65] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add frank.chang
2020-07-10 10:49 ` [RFC 55/65] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf frank.chang
2020-07-10 10:49 ` [RFC 56/65] target/riscv: rvv-0.9: remove integer extract instruction frank.chang
2020-07-10 10:49 ` [RFC 57/65] target/riscv: rvv-0.9: floating-point min/max instructions frank.chang
2020-07-10 18:19 ` Alex Bennée
2020-07-10 10:49 ` [RFC 58/65] target/riscv: rvv-0.9: widening floating-point/integer type-convert frank.chang
2020-07-10 10:49 ` [RFC 59/65] target/riscv: rvv-0.9: narrowing " frank.chang
2020-07-10 10:49 ` [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions frank.chang
2020-07-10 12:07 ` Alex Bennée
2020-07-10 12:15 ` Frank Chang
2020-07-10 12:46 ` Alex Bennée
2020-07-10 13:13 ` Frank Chang
2020-07-10 14:59 ` Alex Bennée
2020-07-10 10:49 ` [RFC 61/65] fpu: fix float16 nan check frank.chang
2020-07-10 10:49 ` [RFC 62/65] fpu: add api to handle alternative sNaN propagation frank.chang
2020-07-10 12:15 ` Alex Bennée
2020-07-13 17:38 ` Chih-Min Chao
2020-07-10 10:49 ` [RFC 63/65] fpu: implement full set compare for fp16 frank.chang
2020-07-10 12:24 ` Alex Bennée
2020-07-10 12:26 ` Alex Bennée
2020-07-14 9:29 ` Chih-Min Chao
2020-07-10 10:49 ` [RFC 64/65] target/riscv: use softfloat lib float16 comparison functions frank.chang
2020-07-10 10:49 ` [RFC 65/65] target/riscv: bump to RVV 0.9 frank.chang
2020-07-10 21:43 ` [RFC 00/65] target/riscv: support vector extension v0.9 Alistair Francis
2020-07-13 2:02 ` Frank Chang
2020-07-13 15:57 ` Alistair Francis
2020-07-13 16:41 ` Richard Henderson
2020-07-13 16:44 ` Frank Chang
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