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d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=T9u1nm+CwLhB5jIRVog43fyVg5RFc3gabjxZL45eFMo=; b=h1j6mrEmCGZ2eg7xAvuuzvfoBbPUxviM8COooQO4OuJaTABqhHkhknsY2YE1AviwTT dQze0u+T6qa4DnMr3tZWlMlBw/fHayNp7XxUzJPJ+lnHvNdOkn2ZVPHu+Gg4YEh/k3Gd 5cPbAMK34LkFPCUImdEVOddaW2S86FN6ImZluqgB2Unyw8jkjyJfIrd6yJuiSeKpJsog bgKgykrXNhCdUra1bC2p/hH1bMz0DKqoct/2c+ulTTEesD91NorQI9Qug/erIsZ85jE0 tSW9XqvywqYTOX52Qg+Uf/PE3ReO943CzKd8RPjVCcTg18XP4m+UtjXPSu4FYBeBIOsQ DGbQ== X-Gm-Message-State: AOAM532bkJ4X/OXzrFMOPO1fLi/C0StgZWoDOkkXd00yWrZPzQNtN7aa ISFXyQOXCycDDP4CnY/qXRuCle09G547RmXhiTfKKA== X-Google-Smtp-Source: ABdhPJyOMYavmsBV/9CNup2HmuAHG4mt4zLcl4ZJXEI7wRxydERQnw+TpJB3bXw8372+e2Msw82cFODJK4MXgaD3jHg= X-Received: by 2002:a05:6e02:b2a:: with SMTP id e10mr6873416ilu.53.1634374371656; Sat, 16 Oct 2021 01:52:51 -0700 (PDT) MIME-Version: 1.0 References: <20211015065500.3850513-1-frank.chang@sifive.com> <20211015065500.3850513-3-frank.chang@sifive.com> <4b718269-b222-c08f-ca72-656bacc31331@linaro.org> In-Reply-To: <4b718269-b222-c08f-ca72-656bacc31331@linaro.org> From: Frank Chang Date: Sat, 16 Oct 2021 16:52:40 +0800 Message-ID: Subject: Re: [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax To: Richard Henderson Content-Type: multipart/alternative; boundary="000000000000da59e705ce746ffb" Received-SPF: pass client-ip=2607:f8b0:4864:20::135; envelope-from=frank.chang@sifive.com; helo=mail-il1-x135.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Bin Meng , "qemu-devel@nongnu.org Developers" , Chih-Min Chao , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000da59e705ce746ffb Content-Type: text/plain; charset="UTF-8" On Sat, Oct 16, 2021 at 1:05 AM Richard Henderson < richard.henderson@linaro.org> wrote: > On 10/14/21 11:54 PM, frank.chang@sifive.com wrote: > > From: Chih-Min Chao > > > > The sNaN propagation behavior has been changed since > > cd20cee7 inhttps://github.com/riscv/riscv-isa-manual > > > > Signed-off-by: Chih-Min Chao > > --- > > target/riscv/fpu_helper.c | 8 ++++---- > > 1 file changed, 4 insertions(+), 4 deletions(-) > > > > diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c > > index 8700516a14c..1472ead2528 100644 > > --- a/target/riscv/fpu_helper.c > > +++ b/target/riscv/fpu_helper.c > > @@ -174,14 +174,14 @@ uint64_t helper_fmin_s(CPURISCVState *env, > uint64_t rs1, uint64_t rs2) > > { > > float32 frs1 = check_nanbox_s(rs1); > > float32 frs2 = check_nanbox_s(rs2); > > - return nanbox_s(float32_minnum(frs1, frs2, &env->fp_status)); > > + return nanbox_s(float32_minnum_noprop(frs1, frs2, &env->fp_status)); > > } > > Don't you need to conditionalize behaviour on the isa revision? > > I will pick the right API based on CPU privilege spec version. Thanks, Frank Chang > > r~ > --000000000000da59e705ce746ffb Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
On Sat, Oct 16, 2021 at 1:05 AM Richard H= enderson <richard.hender= son@linaro.org> wrote:
On 10/14/21 11:54 PM, frank.chang@sifive.com = wrote:
> From: Chih-Min Chao<chihmin.chao@sifive.com>
>
> The sNaN propagation behavior has been changed since
> cd20cee7 inhttps://github.com/riscv/riscv-isa-manual
>
> Signed-off-by: Chih-Min Chao<chihmin.chao@sifive.com>
> ---
>=C2=A0 =C2=A0target/riscv/fpu_helper.c | 8 ++++----
>=C2=A0 =C2=A01 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
> index 8700516a14c..1472ead2528 100644
> --- a/target/riscv/fpu_helper.c
> +++ b/target/riscv/fpu_helper.c
> @@ -174,14 +174,14 @@ uint64_t helper_fmin_s(CPURISCVState *env, uint6= 4_t rs1, uint64_t rs2)
>=C2=A0 =C2=A0{
>=C2=A0 =C2=A0 =C2=A0 =C2=A0float32 frs1 =3D check_nanbox_s(rs1);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0float32 frs2 =3D check_nanbox_s(rs2);
> -=C2=A0 =C2=A0 return nanbox_s(float32_minnum(frs1, frs2, &env->= ;fp_status));
> +=C2=A0 =C2=A0 return nanbox_s(float32_minnum_noprop(frs1, frs2, &= env->fp_status));
>=C2=A0 =C2=A0}

Don't you need to conditionalize behaviour on the isa revision?


I will pick the right API based on CPU= privilege spec version.

Thanks,
Frank C= hang
=C2=A0