Re: [PATCH v3 1/6] target/riscv: zfh: half-precision load and store

[Frank Chang <frank.chang@sifive.com>]

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On Mon, Oct 18, 2021 at 8:03 AM Alistair Francis <alistair23@gmail.com>
wrote:

> On Sat, Oct 16, 2021 at 7:08 PM <frank.chang@sifive.com> wrote:
> >
> > From: Kito Cheng <kito.cheng@sifive.com>
> >
> > Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> > Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> > ---
> >  target/riscv/cpu.c                        |  1 +
> >  target/riscv/cpu.h                        |  1 +
> >  target/riscv/insn32.decode                |  4 ++
> >  target/riscv/insn_trans/trans_rvzfh.c.inc | 65 +++++++++++++++++++++++
> >  target/riscv/translate.c                  |  8 +++
> >  5 files changed, 79 insertions(+)
> >  create mode 100644 target/riscv/insn_trans/trans_rvzfh.c.inc
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 1d69d1887e6..8c579dc297b 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -601,6 +601,7 @@ static Property riscv_cpu_properties[] = {
> >      DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> >      DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> >      DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> > +    DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
>
> This change should be after patch 5. The idea is that we add the
> functionality and then allow users to enable it.
>
> Otherwise:
>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>
> Alistair
>

The reason why I put here is because REQUIRE_ZFH() uses ctx->zfh.
I can separate ext_zfh field in DisasContext into this patch,
and add cfg.ext_zfh in RISCVCPU after patch 5 in my next patchset.

Thanks,
Frank Chang


>
> >      DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> >      DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> >      DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index 9e55b2f5b17..88684e72be1 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -297,6 +297,7 @@ struct RISCVCPU {
> >          bool ext_counters;
> >          bool ext_ifencei;
> >          bool ext_icsr;
> > +        bool ext_zfh;
> >
> >          char *priv_spec;
> >          char *user_spec;
> > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> > index 2f251dac1bb..b36a3d8dbf8 100644
> > --- a/target/riscv/insn32.decode
> > +++ b/target/riscv/insn32.decode
> > @@ -726,3 +726,7 @@ binv       0110100 .......... 001 ..... 0110011 @r
> >  binvi      01101. ........... 001 ..... 0010011 @sh
> >  bset       0010100 .......... 001 ..... 0110011 @r
> >  bseti      00101. ........... 001 ..... 0010011 @sh
> > +
> > +# *** RV32 Zfh Extension ***
> > +flh        ............   ..... 001 ..... 0000111 @i
> > +fsh        .......  ..... ..... 001 ..... 0100111 @s
> > diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc
> b/target/riscv/insn_trans/trans_rvzfh.c.inc
> > new file mode 100644
> > index 00000000000..dad1d703d72
> > --- /dev/null
> > +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
> > @@ -0,0 +1,65 @@
> > +/*
> > + * RISC-V translation routines for the RV64Zfh Standard Extension.
> > + *
> > + * Copyright (c) 2020 Chih-Min Chao, chihmin.chao@sifive.com
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> it
> > + * under the terms and conditions of the GNU General Public License,
> > + * version 2 or later, as published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope it will be useful, but
> WITHOUT
> > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
> License for
> > + * more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> along with
> > + * this program.  If not, see <http://www.gnu.org/licenses/>.
> > + */
> > +
> > +#define REQUIRE_ZFH(ctx) do { \
> > +    if (!ctx->ext_zfh) {      \
> > +        return false;         \
> > +    }                         \
> > +} while (0)
> > +
> > +static bool trans_flh(DisasContext *ctx, arg_flh *a)
> > +{
> > +    TCGv_i64 dest;
> > +    TCGv t0;
> > +
> > +    REQUIRE_FPU;
> > +    REQUIRE_ZFH(ctx);
> > +
> > +    t0 = get_gpr(ctx, a->rs1, EXT_NONE);
> > +    if (a->imm) {
> > +        TCGv temp = temp_new(ctx);
> > +        tcg_gen_addi_tl(temp, t0, a->imm);
> > +        t0 = temp;
> > +    }
> > +
> > +    dest = cpu_fpr[a->rd];
> > +    tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, MO_TEUW);
> > +    gen_nanbox_h(dest, dest);
> > +
> > +    mark_fs_dirty(ctx);
> > +    return true;
> > +}
> > +
> > +static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
> > +{
> > +    TCGv t0;
> > +
> > +    REQUIRE_FPU;
> > +    REQUIRE_ZFH(ctx);
> > +
> > +    t0 = get_gpr(ctx, a->rs1, EXT_NONE);
> > +    if (a->imm) {
> > +        TCGv temp = tcg_temp_new();
> > +        tcg_gen_addi_tl(temp, t0, a->imm);
> > +        t0 = temp;
> > +    }
> > +
> > +    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUW);
> > +
> > +    return true;
> > +}
> > diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> > index d2442f0cf5d..75048149f5a 100644
> > --- a/target/riscv/translate.c
> > +++ b/target/riscv/translate.c
> > @@ -69,6 +69,7 @@ typedef struct DisasContext {
> >      bool w;
> >      bool virt_enabled;
> >      bool ext_ifencei;
> > +    bool ext_zfh;
> >      bool hlsx;
> >      /* vector extension */
> >      bool vill;
> > @@ -118,6 +119,11 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
> >      tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
> >  }
> >
> > +static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in)
> > +{
> > +    tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48));
> > +}
> > +
> >  /*
> >   * A narrow n-bit operation, where n < FLEN, checks that input operands
> >   * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
> > @@ -489,6 +495,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase,
> target_ulong pc)
> >  #include "insn_trans/trans_rvh.c.inc"
> >  #include "insn_trans/trans_rvv.c.inc"
> >  #include "insn_trans/trans_rvb.c.inc"
> > +#include "insn_trans/trans_rvzfh.c.inc"
> >  #include "insn_trans/trans_privileged.c.inc"
> >
> >  /* Include the auto-generated decoder for 16 bit insn */
> > @@ -541,6 +548,7 @@ static void
> riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> >      ctx->misa = env->misa;
> >      ctx->frm = -1;  /* unknown rounding mode */
> >      ctx->ext_ifencei = cpu->cfg.ext_ifencei;
> > +    ctx->ext_zfh = cpu->cfg.ext_zfh;
> >      ctx->vlen = cpu->cfg.vlen;
> >      ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
> >      ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
> > --
> > 2.25.1
> >
> >
>

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