[PATCH v2] target/riscv: Initialize riscv_excp_names[] and riscv_intr_names[] using designated initializer

[PATCH v2] target/riscv: Initialize riscv_excp_names[] and riscv_intr_names[] using designated initializer

[frank.chang]

From: Frank Chang <frank.chang@sifive.com>

Use designated initializers to initialize riscv_excp_names[] and
riscv_intr_names[] so that we don't have to explicitly add "reserved"
items. Also, add the missing trap names: sw_check, hw_error,
virt_illegal_instruction, semihost, s_guest_external, and
counter_overflow.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
 target/riscv/cpu.c | 89 +++++++++++++++++++++++-----------------------
 1 file changed, 45 insertions(+), 44 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index aa58ba8b99a..ee859093f78 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -305,60 +305,61 @@ const char * const riscv_rvv_regnames[] = {
 };
 
 static const char * const riscv_excp_names[] = {
-    "misaligned_fetch",
-    "fault_fetch",
-    "illegal_instruction",
-    "breakpoint",
-    "misaligned_load",
-    "fault_load",
-    "misaligned_store",
-    "fault_store",
-    "user_ecall",
-    "supervisor_ecall",
-    "hypervisor_ecall",
-    "machine_ecall",
-    "exec_page_fault",
-    "load_page_fault",
-    "reserved",
-    "store_page_fault",
-    "double_trap",
-    "reserved",
-    "reserved",
-    "reserved",
-    "guest_exec_page_fault",
-    "guest_load_page_fault",
-    "reserved",
-    "guest_store_page_fault",
+    [RISCV_EXCP_INST_ADDR_MIS] = "misaligned_fetch",
+    [RISCV_EXCP_INST_ACCESS_FAULT] = "fault_fetch",
+    [RISCV_EXCP_ILLEGAL_INST] = "illegal_instruction",
+    [RISCV_EXCP_BREAKPOINT] = "breakpoint",
+    [RISCV_EXCP_LOAD_ADDR_MIS] = "misaligned_load",
+    [RISCV_EXCP_LOAD_ACCESS_FAULT] = "fault_load",
+    [RISCV_EXCP_STORE_AMO_ADDR_MIS] = "misaligned_store",
+    [RISCV_EXCP_STORE_AMO_ACCESS_FAULT] = "fault_store",
+    [RISCV_EXCP_U_ECALL] = "user_ecall",
+    [RISCV_EXCP_S_ECALL] = "supervisor_ecall",
+    [RISCV_EXCP_VS_ECALL] = "hypervisor_ecall",
+    [RISCV_EXCP_M_ECALL] = "machine_ecall",
+    [RISCV_EXCP_INST_PAGE_FAULT] = "exec_page_fault",
+    [RISCV_EXCP_LOAD_PAGE_FAULT] = "load_page_fault",
+    [RISCV_EXCP_STORE_PAGE_FAULT] = "store_page_fault",
+    [RISCV_EXCP_DOUBLE_TRAP] = "double_trap",
+    [RISCV_EXCP_SW_CHECK] = "sw_check",
+    [RISCV_EXCP_HW_ERR] = "hw_error",
+    [RISCV_EXCP_INST_GUEST_PAGE_FAULT] = "guest_exec_page_fault",
+    [RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT] = "guest_load_page_fault",
+    [RISCV_EXCP_VIRT_INSTRUCTION_FAULT] = "virt_illegal_instruction",
+    [RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT] = "guest_store_page_fault",
+    [RISCV_EXCP_SEMIHOST] = "semihost",
 };
 
 static const char * const riscv_intr_names[] = {
-    "u_software",
-    "s_software",
-    "vs_software",
-    "m_software",
-    "u_timer",
-    "s_timer",
-    "vs_timer",
-    "m_timer",
-    "u_external",
-    "s_external",
-    "vs_external",
-    "m_external",
-    "reserved",
-    "reserved",
-    "reserved",
-    "reserved"
+    [IRQ_U_SOFT] = "u_software",
+    [IRQ_S_SOFT] = "s_software",
+    [IRQ_VS_SOFT] = "vs_software",
+    [IRQ_M_SOFT] = "m_software",
+    [IRQ_U_TIMER] = "u_timer",
+    [IRQ_S_TIMER] = "s_timer",
+    [IRQ_VS_TIMER] = "vs_timer",
+    [IRQ_M_TIMER] = "m_timer",
+    [IRQ_U_EXT] = "u_external",
+    [IRQ_S_EXT] = "s_external",
+    [IRQ_VS_EXT] = "vs_external",
+    [IRQ_M_EXT] = "m_external",
+    [IRQ_S_GEXT] = "s_guest_external",
+    [IRQ_PMU_OVF] = "counter_overflow",
 };
 
 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
 {
     if (async) {
-        return (cause < ARRAY_SIZE(riscv_intr_names)) ?
-               riscv_intr_names[cause] : "(unknown)";
+        if ((cause < ARRAY_SIZE(riscv_intr_names)) && riscv_intr_names[cause]) {
+            return riscv_intr_names[cause];
+        }
     } else {
-        return (cause < ARRAY_SIZE(riscv_excp_names)) ?
-               riscv_excp_names[cause] : "(unknown)";
+        if ((cause < ARRAY_SIZE(riscv_excp_names)) && riscv_excp_names[cause]) {
+            return riscv_excp_names[cause];
+        }
     }
+
+    return "(unknown)";
 }
 
 void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext)
-- 
2.43.0

Re: [PATCH v2] target/riscv: Initialize riscv_excp_names[] and riscv_intr_names[] using designated initializer

[Philippe Mathieu-Daudé]

On 19/12/25 05:09, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
> 
> Use designated initializers to initialize riscv_excp_names[] and
> riscv_intr_names[] so that we don't have to explicitly add "reserved"
> items. Also, add the missing trap names: sw_check, hw_error,
> virt_illegal_instruction, semihost, s_guest_external, and
> counter_overflow.
> 
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Max Chou <max.chou@sifive.com>
> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> ---
>   target/riscv/cpu.c | 89 +++++++++++++++++++++++-----------------------
>   1 file changed, 45 insertions(+), 44 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Re: [PATCH v2] target/riscv: Initialize riscv_excp_names[] and riscv_intr_names[] using designated initializer

[Nutty.Liu]

On 12/19/2025 12:09 PM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> Use designated initializers to initialize riscv_excp_names[] and
> riscv_intr_names[] so that we don't have to explicitly add "reserved"
> items. Also, add the missing trap names: sw_check, hw_error,
> virt_illegal_instruction, semihost, s_guest_external, and
> counter_overflow.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Max Chou <max.chou@sifive.com>
> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> ---
>   target/riscv/cpu.c | 89 +++++++++++++++++++++++-----------------------
>   1 file changed, 45 insertions(+), 44 deletions(-)
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>

Thanks,
Nutty

Re: [PATCH v2] target/riscv: Initialize riscv_excp_names[] and riscv_intr_names[] using designated initializer

[Frank Chang]

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Gentle ping

Thanks,
Frank Chang

On Fri, Dec 19, 2025 at 12:09 PM <frank.chang@sifive.com> wrote:

> From: Frank Chang <frank.chang@sifive.com>
>
> Use designated initializers to initialize riscv_excp_names[] and
> riscv_intr_names[] so that we don't have to explicitly add "reserved"
> items. Also, add the missing trap names: sw_check, hw_error,
> virt_illegal_instruction, semihost, s_guest_external, and
> counter_overflow.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Max Chou <max.chou@sifive.com>
> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> ---
>  target/riscv/cpu.c | 89 +++++++++++++++++++++++-----------------------
>  1 file changed, 45 insertions(+), 44 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index aa58ba8b99a..ee859093f78 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -305,60 +305,61 @@ const char * const riscv_rvv_regnames[] = {
>  };
>
>  static const char * const riscv_excp_names[] = {
> -    "misaligned_fetch",
> -    "fault_fetch",
> -    "illegal_instruction",
> -    "breakpoint",
> -    "misaligned_load",
> -    "fault_load",
> -    "misaligned_store",
> -    "fault_store",
> -    "user_ecall",
> -    "supervisor_ecall",
> -    "hypervisor_ecall",
> -    "machine_ecall",
> -    "exec_page_fault",
> -    "load_page_fault",
> -    "reserved",
> -    "store_page_fault",
> -    "double_trap",
> -    "reserved",
> -    "reserved",
> -    "reserved",
> -    "guest_exec_page_fault",
> -    "guest_load_page_fault",
> -    "reserved",
> -    "guest_store_page_fault",
> +    [RISCV_EXCP_INST_ADDR_MIS] = "misaligned_fetch",
> +    [RISCV_EXCP_INST_ACCESS_FAULT] = "fault_fetch",
> +    [RISCV_EXCP_ILLEGAL_INST] = "illegal_instruction",
> +    [RISCV_EXCP_BREAKPOINT] = "breakpoint",
> +    [RISCV_EXCP_LOAD_ADDR_MIS] = "misaligned_load",
> +    [RISCV_EXCP_LOAD_ACCESS_FAULT] = "fault_load",
> +    [RISCV_EXCP_STORE_AMO_ADDR_MIS] = "misaligned_store",
> +    [RISCV_EXCP_STORE_AMO_ACCESS_FAULT] = "fault_store",
> +    [RISCV_EXCP_U_ECALL] = "user_ecall",
> +    [RISCV_EXCP_S_ECALL] = "supervisor_ecall",
> +    [RISCV_EXCP_VS_ECALL] = "hypervisor_ecall",
> +    [RISCV_EXCP_M_ECALL] = "machine_ecall",
> +    [RISCV_EXCP_INST_PAGE_FAULT] = "exec_page_fault",
> +    [RISCV_EXCP_LOAD_PAGE_FAULT] = "load_page_fault",
> +    [RISCV_EXCP_STORE_PAGE_FAULT] = "store_page_fault",
> +    [RISCV_EXCP_DOUBLE_TRAP] = "double_trap",
> +    [RISCV_EXCP_SW_CHECK] = "sw_check",
> +    [RISCV_EXCP_HW_ERR] = "hw_error",
> +    [RISCV_EXCP_INST_GUEST_PAGE_FAULT] = "guest_exec_page_fault",
> +    [RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT] = "guest_load_page_fault",
> +    [RISCV_EXCP_VIRT_INSTRUCTION_FAULT] = "virt_illegal_instruction",
> +    [RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT] = "guest_store_page_fault",
> +    [RISCV_EXCP_SEMIHOST] = "semihost",
>  };
>
>  static const char * const riscv_intr_names[] = {
> -    "u_software",
> -    "s_software",
> -    "vs_software",
> -    "m_software",
> -    "u_timer",
> -    "s_timer",
> -    "vs_timer",
> -    "m_timer",
> -    "u_external",
> -    "s_external",
> -    "vs_external",
> -    "m_external",
> -    "reserved",
> -    "reserved",
> -    "reserved",
> -    "reserved"
> +    [IRQ_U_SOFT] = "u_software",
> +    [IRQ_S_SOFT] = "s_software",
> +    [IRQ_VS_SOFT] = "vs_software",
> +    [IRQ_M_SOFT] = "m_software",
> +    [IRQ_U_TIMER] = "u_timer",
> +    [IRQ_S_TIMER] = "s_timer",
> +    [IRQ_VS_TIMER] = "vs_timer",
> +    [IRQ_M_TIMER] = "m_timer",
> +    [IRQ_U_EXT] = "u_external",
> +    [IRQ_S_EXT] = "s_external",
> +    [IRQ_VS_EXT] = "vs_external",
> +    [IRQ_M_EXT] = "m_external",
> +    [IRQ_S_GEXT] = "s_guest_external",
> +    [IRQ_PMU_OVF] = "counter_overflow",
>  };
>
>  const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
>  {
>      if (async) {
> -        return (cause < ARRAY_SIZE(riscv_intr_names)) ?
> -               riscv_intr_names[cause] : "(unknown)";
> +        if ((cause < ARRAY_SIZE(riscv_intr_names)) &&
> riscv_intr_names[cause]) {
> +            return riscv_intr_names[cause];
> +        }
>      } else {
> -        return (cause < ARRAY_SIZE(riscv_excp_names)) ?
> -               riscv_excp_names[cause] : "(unknown)";
> +        if ((cause < ARRAY_SIZE(riscv_excp_names)) &&
> riscv_excp_names[cause]) {
> +            return riscv_excp_names[cause];
> +        }
>      }
> +
> +    return "(unknown)";
>  }
>
>  void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext)
> --
> 2.43.0
>
>

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