* [PATCH] target/riscv: Remove .min_priv_ver restriction from RVV CSRs
@ 2023-02-07 8:43 frank.chang
2023-02-07 9:43 ` Bin Meng
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: frank.chang @ 2023-02-07 8:43 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, Frank Chang, Palmer Dabbelt, Alistair Francis,
Bin Meng
From: Frank Chang <frank.chang@sifive.com>
The RVV specification does not require that the core needs to support
the privileged specification v1.12.0 to support RVV, and there is no
dependency from ISA level. This commit removes the restriction.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/csr.c | 21 +++++++--------------
1 file changed, 7 insertions(+), 14 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index fa17d7770c4..1b0a0c1693c 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3980,20 +3980,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_FRM] = { "frm", fs, read_frm, write_frm },
[CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr },
/* Vector CSRs */
- [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart,
- .min_priv_ver = PRIV_VERSION_1_12_0 },
- [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat,
- .min_priv_ver = PRIV_VERSION_1_12_0 },
- [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm,
- .min_priv_ver = PRIV_VERSION_1_12_0 },
- [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr,
- .min_priv_ver = PRIV_VERSION_1_12_0 },
- [CSR_VL] = { "vl", vs, read_vl,
- .min_priv_ver = PRIV_VERSION_1_12_0 },
- [CSR_VTYPE] = { "vtype", vs, read_vtype,
- .min_priv_ver = PRIV_VERSION_1_12_0 },
- [CSR_VLENB] = { "vlenb", vs, read_vlenb,
- .min_priv_ver = PRIV_VERSION_1_12_0 },
+ [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart },
+ [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat },
+ [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm },
+ [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr },
+ [CSR_VL] = { "vl", vs, read_vl },
+ [CSR_VTYPE] = { "vtype", vs, read_vtype },
+ [CSR_VLENB] = { "vlenb", vs, read_vlenb },
/* User Timers and Counters */
[CSR_CYCLE] = { "cycle", ctr, read_hpmcounter },
[CSR_INSTRET] = { "instret", ctr, read_hpmcounter },
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] target/riscv: Remove .min_priv_ver restriction from RVV CSRs
2023-02-07 8:43 [PATCH] target/riscv: Remove .min_priv_ver restriction from RVV CSRs frank.chang
@ 2023-02-07 9:43 ` Bin Meng
2023-02-08 1:16 ` LIU Zhiwei
2023-02-08 6:30 ` Frank Chang
2 siblings, 0 replies; 4+ messages in thread
From: Bin Meng @ 2023-02-07 9:43 UTC (permalink / raw)
To: frank.chang
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng
On Tue, Feb 7, 2023 at 4:45 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> The RVV specification does not require that the core needs to support
> the privileged specification v1.12.0 to support RVV, and there is no
> dependency from ISA level. This commit removes the restriction.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/csr.c | 21 +++++++--------------
> 1 file changed, 7 insertions(+), 14 deletions(-)
>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv: Remove .min_priv_ver restriction from RVV CSRs
2023-02-07 8:43 [PATCH] target/riscv: Remove .min_priv_ver restriction from RVV CSRs frank.chang
2023-02-07 9:43 ` Bin Meng
@ 2023-02-08 1:16 ` LIU Zhiwei
2023-02-08 6:30 ` Frank Chang
2 siblings, 0 replies; 4+ messages in thread
From: LIU Zhiwei @ 2023-02-08 1:16 UTC (permalink / raw)
To: frank.chang, qemu-devel
Cc: qemu-riscv, Palmer Dabbelt, Alistair Francis, Bin Meng
On 2023/2/7 16:43, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> The RVV specification does not require that the core needs to support
> the privileged specification v1.12.0 to support RVV, and there is no
> dependency from ISA level. This commit removes the restriction.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/csr.c | 21 +++++++--------------
> 1 file changed, 7 insertions(+), 14 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index fa17d7770c4..1b0a0c1693c 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3980,20 +3980,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_FRM] = { "frm", fs, read_frm, write_frm },
> [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr },
> /* Vector CSRs */
> - [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart,
> - .min_priv_ver = PRIV_VERSION_1_12_0 },
> - [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat,
> - .min_priv_ver = PRIV_VERSION_1_12_0 },
> - [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm,
> - .min_priv_ver = PRIV_VERSION_1_12_0 },
> - [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr,
> - .min_priv_ver = PRIV_VERSION_1_12_0 },
> - [CSR_VL] = { "vl", vs, read_vl,
> - .min_priv_ver = PRIV_VERSION_1_12_0 },
> - [CSR_VTYPE] = { "vtype", vs, read_vtype,
> - .min_priv_ver = PRIV_VERSION_1_12_0 },
> - [CSR_VLENB] = { "vlenb", vs, read_vlenb,
> - .min_priv_ver = PRIV_VERSION_1_12_0 },
> + [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart },
> + [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat },
> + [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm },
> + [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr },
> + [CSR_VL] = { "vl", vs, read_vl },
> + [CSR_VTYPE] = { "vtype", vs, read_vtype },
> + [CSR_VLENB] = { "vlenb", vs, read_vlenb },
> /* User Timers and Counters */
> [CSR_CYCLE] = { "cycle", ctr, read_hpmcounter },
> [CSR_INSTRET] = { "instret", ctr, read_hpmcounter },
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Zhiwei
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] target/riscv: Remove .min_priv_ver restriction from RVV CSRs
2023-02-07 8:43 [PATCH] target/riscv: Remove .min_priv_ver restriction from RVV CSRs frank.chang
2023-02-07 9:43 ` Bin Meng
2023-02-08 1:16 ` LIU Zhiwei
@ 2023-02-08 6:30 ` Frank Chang
2 siblings, 0 replies; 4+ messages in thread
From: Frank Chang @ 2023-02-08 6:30 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, Palmer Dabbelt, Alistair Francis, Bin Meng
[-- Attachment #1: Type: text/plain, Size: 2750 bytes --]
I realized that I should also remove the privileged version check
in isa_edata_arr[], too.
I will send out v2 patch to fix it.
Regards,
Frank Chang
On Tue, Feb 7, 2023 at 4:43 PM <frank.chang@sifive.com> wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> The RVV specification does not require that the core needs to support
> the privileged specification v1.12.0 to support RVV, and there is no
> dependency from ISA level. This commit removes the restriction.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/csr.c | 21 +++++++--------------
> 1 file changed, 7 insertions(+), 14 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index fa17d7770c4..1b0a0c1693c 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3980,20 +3980,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_FRM] = { "frm", fs, read_frm, write_frm },
> [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr },
> /* Vector CSRs */
> - [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart,
> - .min_priv_ver = PRIV_VERSION_1_12_0 },
> - [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat,
> - .min_priv_ver = PRIV_VERSION_1_12_0 },
> - [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm,
> - .min_priv_ver = PRIV_VERSION_1_12_0 },
> - [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr,
> - .min_priv_ver = PRIV_VERSION_1_12_0 },
> - [CSR_VL] = { "vl", vs, read_vl,
> - .min_priv_ver = PRIV_VERSION_1_12_0 },
> - [CSR_VTYPE] = { "vtype", vs, read_vtype,
> - .min_priv_ver = PRIV_VERSION_1_12_0 },
> - [CSR_VLENB] = { "vlenb", vs, read_vlenb,
> - .min_priv_ver = PRIV_VERSION_1_12_0 },
> + [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart },
> + [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat },
> + [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm },
> + [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr },
> + [CSR_VL] = { "vl", vs, read_vl },
> + [CSR_VTYPE] = { "vtype", vs, read_vtype },
> + [CSR_VLENB] = { "vlenb", vs, read_vlenb },
> /* User Timers and Counters */
> [CSR_CYCLE] = { "cycle", ctr, read_hpmcounter },
> [CSR_INSTRET] = { "instret", ctr, read_hpmcounter },
> --
> 2.25.1
>
>
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2023-02-07 8:43 [PATCH] target/riscv: Remove .min_priv_ver restriction from RVV CSRs frank.chang
2023-02-07 9:43 ` Bin Meng
2023-02-08 1:16 ` LIU Zhiwei
2023-02-08 6:30 ` Frank Chang
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