From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2FB9C433E0 for ; Mon, 13 Jul 2020 02:07:56 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BFA63206D9 for ; Mon, 13 Jul 2020 02:07:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="jwW4NF3Z" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BFA63206D9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:58284 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1junsq-0004BS-1O for qemu-devel@archiver.kernel.org; Sun, 12 Jul 2020 22:07:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34698) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1junsH-0003kh-89 for qemu-devel@nongnu.org; Sun, 12 Jul 2020 22:07:21 -0400 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]:33506) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1junsF-0007eg-Ei for qemu-devel@nongnu.org; Sun, 12 Jul 2020 22:07:20 -0400 Received: by mail-oi1-x22b.google.com with SMTP id k22so9809608oib.0 for ; Sun, 12 Jul 2020 19:07:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ABw3Z3OuvCTl1fggcJHqjIgqh/IW2fOK0CJY+oyqysQ=; b=jwW4NF3Z3zVAgijcZmCN8FSH3odlPu1g808q/y/oDvILd9ixZo2TdgHktDeZpdCzsZ nzi6ZBSuSMYEnTBp4cOv9zQgEgrSeLTYiDu3QDra03DSUsllrNH71bG9EJwmOYeGOj6c 07r1st4ud/p4AR0x1v9L4kp2HxUsA5G25Ex6DPShVnC4SAHkznEmuvKP+6up1r4Kfq9M RTr4I/AIPGaK+yD4uFU3KpLcmF1eGo1II0LTJQQE+5O9wlH/aVZBP05ktaDqJYOjkNq2 5ePutC1VVCqhQvgPvmTP2zClCM9jXhCfEEFV/8XEt10IMEZ+d/+CGMUsQFB3peINEngT fAHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ABw3Z3OuvCTl1fggcJHqjIgqh/IW2fOK0CJY+oyqysQ=; b=AHQQlBoaZ1Ey/NaQ2Ll8Gg0ektdUMJ5wZn6Koio7MlnBP1oDIihqhaZAGscL29OSS/ +6GrAkc4qT93Fpv9yizxodufUsAp3+DztURR6ELO0alikHsLqpY0dSAQ3LFvZG96AwwU gtePwxmpPCeSBcXA1aAus4FdePx2acqC4gwz/kkEyHQTpgFfCByqyk4u+MuDpu48oHHq /Gs6+MEaLiGN9TCpxlRrjAkVV/N5857XWzsc12ZrPrWedcqnACWPDKFQ0EDPcIneti2i 72i8AgYDME5mK//vJRmK3Pbl1f+Pispt+zqG6tbc7A1aeMdpZzD3yTIErOqRuUOFvScI BojQ== X-Gm-Message-State: AOAM533fGCPWuDeSjIzqSD2p5iWcJZBpfpXM3QyTVy1yy4HqN/u0N6VQ +Vn/V8DE2+pMcPaErDEDD1RXCrDFskRapiuSqs2UVQ== X-Google-Smtp-Source: ABdhPJy0ojkQKo0eSoLHsaA1vv/mwPn8WhkthBzbrq19t+voyqnbwWhaTV/sfMs8+a0LNxw48KY+CIuUIxiXHTTZJ5U= X-Received: by 2002:aca:b203:: with SMTP id b3mr11918689oif.118.1594606038369; Sun, 12 Jul 2020 19:07:18 -0700 (PDT) MIME-Version: 1.0 References: <20200710104920.13550-1-frank.chang@sifive.com> <20200710104920.13550-14-frank.chang@sifive.com> In-Reply-To: From: Frank Chang Date: Mon, 13 Jul 2020 10:07:07 +0800 Message-ID: Subject: Re: [RFC 13/65] target/riscv: rvv-0.9: configure instructions To: Richard Henderson Content-Type: multipart/alternative; boundary="0000000000007950e805aa49260f" Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=frank.chang@sifive.com; helo=mail-oi1-x22b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Sagar Karandikar , Bastian Koppelmann , qemu-devel@nongnu.org, Palmer Dabbelt , Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --0000000000007950e805aa49260f Content-Type: text/plain; charset="UTF-8" On Sat, Jul 11, 2020 at 2:07 AM Richard Henderson < richard.henderson@linaro.org> wrote: > On 7/10/20 3:48 AM, frank.chang@sifive.com wrote: > > -static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a) > > +static bool trans_vsetvl(DisasContext *s, arg_vsetvl *a) > > Do not mix this change with anything else. OK~ --- Frank Chang > > + rd = tcg_const_i32(a->rd); > > + rs1 = tcg_const_i32(a->rs1); > > Any time you put a register number into a tcg const, there's probably a > better > way to do things. > > - /* Using x0 as the rs1 register specifier, encodes an infinite AVL > */ > > - if (a->rs1 == 0) { > > - /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */ > > - s1 = tcg_const_tl(RV_VLEN_MAX); > > - } else { > > - s1 = tcg_temp_new(); > > - gen_get_gpr(s1, a->rs1); > > - } > > E.g. this code should be kept, and add > > if (a->rd == 0 && a->rs1 == 0) { > s1 = tcg_temp_new(); > tcg_gen_mov_tl(s1, cpu_vl); > } else ... > OK~ > > > + if ((sew > cpu->cfg.elen) > > + || vill > > + || vflmul < ((float)sew / cpu->cfg.elen) > > + || (ediv != 0) > > + || (reserved != 0)) { > > /* only set vill bit. */ > > env->vtype = FIELD_DP64(0, VTYPE, VILL, 1); > > - env->vl = 0; > > - env->vstart = 0; > > return 0; > > } > > You do need to check 0.7.1 so long as it's supported. > > > r~ > Will drop 0.7.1 support in my first patch to prevent the confusion. Frank Chang --0000000000007950e805aa49260f Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
On Sat, Jul 11, 2020 at 2:07 AM Richard H= enderson <richard.hender= son@linaro.org> wrote:
On 7/10/20 3:48 AM, frank.chang@sifive.com wr= ote:
> -static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
> +static bool trans_vsetvl(DisasContext *s, arg_vsetvl *a)

Do not mix this change with anything else.
=C2=A0
OK~
---
Frank Chang


> +=C2=A0 =C2=A0 rd =3D tcg_const_i32(a->rd);
> +=C2=A0 =C2=A0 rs1 =3D tcg_const_i32(a->rs1);

Any time you put a register number into a tcg const, there's probably a= better
way to do things.

> -=C2=A0 =C2=A0 /* Using x0 as the rs1 register specifier, encodes an i= nfinite AVL */
> -=C2=A0 =C2=A0 if (a->rs1 =3D=3D 0) {
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* As the mask is at least one bit, RV_VL= EN_MAX is >=3D VLMAX */
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 s1 =3D tcg_const_tl(RV_VLEN_MAX);
> -=C2=A0 =C2=A0 } else {
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 s1 =3D tcg_temp_new();
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 gen_get_gpr(s1, a->rs1);
> -=C2=A0 =C2=A0 }

E.g. this code should be kept, and add

=C2=A0 =C2=A0 if (a->rd =3D=3D 0 && a->rs1 =3D=3D 0) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 s1 =3D tcg_temp_new();
=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_mov_tl(s1, cpu_vl);
=C2=A0 =C2=A0 } else ...
OK~

> +=C2=A0 =C2=A0 if ((sew > cpu->cfg.elen)
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 || vill
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 || vflmul < ((float)sew / cpu->cfg.= elen)
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 || (ediv !=3D 0)
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 || (reserved !=3D 0)) {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* only set vill bit. */
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 env->vtype =3D FIELD_DP64(0, VTYP= E, VILL, 1);
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->vl =3D 0;
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->vstart =3D 0;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return 0;
>=C2=A0 =C2=A0 =C2=A0 }

You do need to check 0.7.1 so long as it's supported.


r~

Will drop 0.7.1 support in my first = patch to prevent the confusion.=C2=A0

Frank Chang<= /div>
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