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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=christoph.muellner@vrull.eu; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Mar 28, 2024 at 2:19=E2=80=AFAM Alistair Francis wrote: > > On Wed, Mar 27, 2024 at 9:19=E2=80=AFPM Conor Dooley w= rote: > > > > Christoph linked here on his submission to Linux of a fix for this, so = I > > am reviving this to leave a couple comments :) > > > > On Thu, Feb 15, 2024 at 02:24:02PM +1000, Alistair Francis wrote: > > > On Mon, Feb 5, 2024 at 6:37=E2=80=AFPM Christoph M=C3=BCllner > > > wrote: > > > > On Mon, Feb 5, 2024 at 3:42=E2=80=AFAM Alistair Francis wrote: > > > > > On Sun, Feb 4, 2024 at 3:44=E2=80=AFPM LIU Zhiwei wrote: > > > > > > > > ppn =3D (pte & (target_ulong)PTE_PPN_MASK) >> PTE_= PPN_SHIFT; > > > > > > > > > > Unfortunately we won't be able to take this upstream. This is cor= e > > > > > QEMU RISC-V code that is now being changed against the spec. I th= ink > > > > > adding the CSR is fine, but we can't take this core change. > > > > > > > > > > A fix that works for everyone should be supporting the th_mxstatu= s > > > > > CSR, but don't support setting the TH_MXSTATUS_MAEE bit. That way > > > > > guests can detect that the bit isn't set and not use the reserved= bits > > > > > in the PTE. From my understanding the extra PTE bits are related = to > > > > > cache control in the hardware, which we don't need here > > > > > > > > Sounds good! Let me recap the overall plan: > > > > * QEMU does not emulate MAEE, but signals that MAEE is not availabl= e > > > > by setting TH_MXSTATUS_MAEE to 0. > > > > > > Yep! > > > > > > > * Consequence: The c906 emulation does not enable any page-base mem= ory > > > > attribute mechanism. > > > > > > Exactly > > > > > > > * OpenSBI tests the TH_MXSTATUS_MAEE bit (M-mode only) and provides > > > > that information to user-space (e.g. DTB). > > > > > > To the kernel, but yep! > > > > > > > * The current Linux errata code will be enhanced to not assume MAEE > > > > for each core with T-Head vendor ID, but also query the MAEE bit an= d > > > > ensure it is set. > > > > > > I feel like it should already do that :) > > > > It doesn't quite do this right now. It only makes the assumption for > > CPUs where marchid and mvendorid are zero. The c908, and I think Guo Re= n > > confirmed it will be the case going forward, sets these to non-zero > > values. We should have always required a dt property be set, rather tha= n > > using m*id, but we can't go back on that for these devices. Going > > forward, if there are more CPUs that want to use this e.g. C908 in MAEE > > mode (it can do svpbmt too) I'm gonna require it is explicitly set in > > A DT node that we don't set also works fine for us I would really like to do that, but given the page table is set up so early in the boot process probing via CSR is much easier to realize in the kernel than parsing the DT= . Therefore, I think th.sxstatus emulation + probing is the best way to move forward. Thanks, Christoph