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bh=tvV1xbzdJ1qrB8VSQ3beecMlFs7an2DDX2DOuueZ974=; b=WIjRpq8Rm3ZxMB6IIHXAAiB7VcxZcHz2Y8BKHabNxvmG0EzFNR4u3onjNIeL93eqJ3 hThm9X5KEWfFYX4gE9W1icy/Br0qYc+DBck3VneU747f/Dgzbp33nCnFzruu3xuoYN++ 6ab5WbS91pEBD05PFldsNMTyF0NiNc5qq5qQ12YKaJCueBZqxaIUHGlf+wLDexpE5Glx vwzq+/7+8N1zVXOe3iqmmy6b/OjuCNmgQ4bahtkXHKT1VrKHoVo66IvqQYzQMAnjKSg4 0sEW2wI7yS46vExOA8YyHnc7e2pea0oOFCFMtCYuKEbBo4goYXfd3ZxFIZmRRo9cHHi4 Ry6g== X-Gm-Message-State: ABy/qLaNkFBdDACY4J6WgC0aMLWh+6zmj0oehVkOzW+ZTc+krm51nB/0 vvCanOZ3579zN3LcremE3wRvWqM/Sk4MTMdRtZ2F0w== X-Google-Smtp-Source: APBJJlEYb+0M0xHbM0J0tFDrD0+cD5nFicDie80WQsIjg/IHH2h7sM2nAEIyPKtV3m+oYeRZfRuvtEGAEaugKf10zdU= X-Received: by 2002:adf:fec3:0:b0:314:1318:18b7 with SMTP id q3-20020adffec3000000b00314131818b7mr1348020wrs.19.1688118964430; Fri, 30 Jun 2023 02:56:04 -0700 (PDT) MIME-Version: 1.0 References: <20230630091303.1676486-1-christoph.muellner@vrull.eu> <20230630091303.1676486-3-christoph.muellner@vrull.eu> <599e9042-4e58-d468-940c-f8a8ee1edf5d@linaro.org> In-Reply-To: <599e9042-4e58-d468-940c-f8a8ee1edf5d@linaro.org> From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Fri, 30 Jun 2023 11:55:51 +0200 Message-ID: Subject: Re: [PATCH v4 2/3] target/riscv: Use float64_to_int64_modulo for fcvtmod.w.d To: Richard Henderson Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , Palmer Dabbelt , Jeff Law , Tsukasa OI , liweiwei@iscas.ac.cn, Daniel Henrique Barboza , Liu Zhiwei , Rob Bradford Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=christoph.muellner@vrull.eu; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Jun 30, 2023 at 11:22=E2=80=AFAM Richard Henderson wrote: > > On 6/30/23 11:13, Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > > > For the most part we can use the new generic routine, > > though exceptions need some post-processing. > > > > Signed-off-by: Christoph M=C3=BCllner > > --- > > target/riscv/fpu_helper.c | 78 ++++++++++++++------------------------= - > > 1 file changed, 27 insertions(+), 51 deletions(-) > > > > diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c > > index 289b3bbea5..0f897cf072 100644 > > --- a/target/riscv/fpu_helper.c > > +++ b/target/riscv/fpu_helper.c > > @@ -482,70 +482,46 @@ target_ulong helper_fcvt_w_d(CPURISCVState *env, = uint64_t frs1) > > return float64_to_int32(frs1, &env->fp_status); > > } > > > > +/* T floating (double) */ > > +static inline float64 t_to_float64(uint64_t a) > > +{ > > + /* Memory format is the same as float64 */ > > + CPU_DoubleU r; > > + r.ll =3D a; > > + return r.d; > > +} > > You don't need this. Nor does Alpha anymore, come to that. > float64 is uint64_t now, always. Ok. > > > + int64_t ret; > > + int32_t ret32; > > + uint32_t e_old, e_new; > > + float64 fvalue; > > + > > + e_old =3D get_float_exception_flags(status); > > + set_float_exception_flags(0, status); > > + fvalue =3D t_to_float64(value); > > + ret =3D float64_to_int32_modulo(fvalue, float_round_to_zero, statu= s); > > + e_new =3D get_float_exception_flags(status); > > + > > + /* Map the flags to the specified ones. */ > > + if (e_new & float_flag_inexact) { > > + e_new =3D float_flag_inexact; > > + } else if (e_new) { > > + e_new =3D float_flag_invalid; > > } > > Why? Generic code will not set both inexact and invalid. > So this is a nop. > > Removing that, all of your fp flags handling can go away. I added that because float64_to_int32_modulo() might also set float_flag_invalid_cvti. I just realized that it is not needed, because riscv_cpu_get_fflags() takes care to not expose flags that are not defined for RISC-V. > > > > /* Truncate to 32-bits. */ > > - int32_t ret32 =3D (int32_t)ret; > > + ret32 =3D (int32_t)ret; > > > > /* If the truncation drops bits then raise NV. */ > > if ((uint64_t)ret32 !=3D ret) > > This will never fail, because you used float64_to_int32_modulo, which alr= eady returns int32_t. > > But we have already raised invalid for overflow, so this can go away as w= ell. Understood. > > Finally, this patch must be merged with the previous, which introduced th= is function. Ok. Thanks! > > > r~