From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46576) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YlMps-0005e0-Uq for qemu-devel@nongnu.org; Thu, 23 Apr 2015 15:30:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YlMpp-0001WY-NW for qemu-devel@nongnu.org; Thu, 23 Apr 2015 15:30:56 -0400 Received: from mail-qg0-f45.google.com ([209.85.192.45]:35999) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YlMpp-0001WT-KN for qemu-devel@nongnu.org; Thu, 23 Apr 2015 15:30:53 -0400 Received: by qgeb100 with SMTP id b100so12991247qge.3 for ; Thu, 23 Apr 2015 12:30:53 -0700 (PDT) MIME-Version: 1.0 Sender: peter.crosthwaite@petalogix.com In-Reply-To: References: <3e026b514473978a9a68cf272a24a52c30bed437.1427108387.git.peter.crosthwaite@xilinx.com> Date: Thu, 23 Apr 2015 12:30:52 -0700 Message-ID: From: Peter Crosthwaite Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH target-arm v4 04/16] arm: Introduce Xilinx ZynqMP SoC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Edgar Iglesias , Ryota Ozaki , "michals@xilinx.com" , QEMU Developers , zach.pfeffer@xilinx.com On Thu, Apr 23, 2015 at 10:47 AM, Peter Maydell wrote: > On 23 March 2015 at 11:05, Peter Crosthwaite > wrote: >> +static void xlnx_zynqmp_init(Object *obj) >> +{ >> + XlnxZynqMPState *s = XLNX_ZYNQMP(obj); >> + int i; >> + >> + for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) { >> + object_initialize(&s->cpu[i], sizeof(s->cpu[i]), >> + "cortex-a53-" TYPE_ARM_CPU); >> + object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpu[i]), >> + &error_abort); >> + } >> +} > >> +static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) >> +{ >> + XlnxZynqMPState *s = XLNX_ZYNQMP(dev); >> + uint8_t i; >> + Error *err = NULL; >> + >> + for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) { >> + object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); >> + ERR_PROP_CHECK_RETURN(err, errp); >> + } >> +} > > This seems to be a touch short on CPU property setting. > I would expect you want most or all of: > * has_el3 has_el3 defines to true by default and the SoC does support EL3. DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); > * psci-conduit > * start-powered-off for the secondaries Squashed in P16. > * reset-cbar Adding to GIC patch. Regards, Peter > > (Some of those may be new in master since this series was posted.) > > thanks > -- PMM >