From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
To: Sergey Fedorov <s.fedorov@samsung.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
a.basov@samsung.com,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
johannes.winter@iaik.tugraz.at,
Svetlana Fedoseeva <s.fedoseeva@samsung.com>
Subject: Re: [Qemu-devel] [RFC PATCH 04/21] target-arm: preserve RAO/WI bits of ARMv7 SCTLR
Date: Tue, 3 Dec 2013 22:17:26 +1000 [thread overview]
Message-ID: <CAEgOgz6mRSnhLBptuM=t_L3cTeiNHH25YpbLvyrwRQM+1DmPCw@mail.gmail.com> (raw)
In-Reply-To: <1386060535-15908-5-git-send-email-s.fedorov@samsung.com>
On Tue, Dec 3, 2013 at 6:48 PM, Sergey Fedorov <s.fedorov@samsung.com> wrote:
> From: Svetlana Fedoseeva <s.fedoseeva@samsung.com>
>
> Signed-off-by: Svetlana Fedoseeva <s.fedoseeva@samsung.com>
> Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com>
> ---
> target-arm/helper.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 6642e53..d7922ad 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1507,6 +1507,10 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
>
> static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
> {
> + if (arm_feature(env, ARM_FEATURE_V7)) {
> + value = value | 0x00c50078; /* This bits are RAO/WI */
Magic number. "these bits ".
> + }
> +
> env->cp15.c1_sys = value;
> /* ??? Lots of these bits are not implemented. */
> /* This may enable/disable the MMU, so do a TLB flush. */
> --
> 1.7.9.5
>
>
next prev parent reply other threads:[~2013-12-03 12:17 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-03 8:48 [Qemu-devel] [RFC PATCH 00/21] target-arm: add CPU core TrustZone support Sergey Fedorov
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 01/21] target-arm: add TrustZone CPU feature Sergey Fedorov
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 02/21] target-arm: move SCR & VBAR into TrustZone register list Sergey Fedorov
2013-12-19 3:12 ` Peter Crosthwaite
2013-12-19 6:23 ` Fedorov Sergey
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 03/21] target-arm: adjust TTBCR for TrustZone feature Sergey Fedorov
2013-12-03 12:15 ` Peter Crosthwaite
2013-12-04 9:50 ` Fedorov Sergey
2013-12-04 10:52 ` Peter Crosthwaite
2013-12-19 3:18 ` Peter Crosthwaite
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 04/21] target-arm: preserve RAO/WI bits of ARMv7 SCTLR Sergey Fedorov
2013-12-03 12:17 ` Peter Crosthwaite [this message]
2013-12-04 9:55 ` Fedorov Sergey
2013-12-19 3:19 ` Peter Crosthwaite
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 05/21] target-arm: add CPU Monitor mode Sergey Fedorov
2013-12-03 12:20 ` Peter Crosthwaite
2013-12-03 12:51 ` Peter Maydell
2013-12-04 10:01 ` Fedorov Sergey
2013-12-04 10:58 ` Peter Crosthwaite
2013-12-04 11:18 ` Peter Maydell
2013-12-04 12:33 ` Fedorov Sergey
2013-12-04 12:35 ` Peter Maydell
2013-12-19 3:26 ` Peter Crosthwaite
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 06/21] target-arm: add arm_is_secure() helper Sergey Fedorov
2013-12-19 3:31 ` Peter Crosthwaite
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 07/21] target-arm: reject switching to monitor mode from non-secure state Sergey Fedorov
2013-12-19 3:44 ` Peter Crosthwaite
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 08/21] target-arm: adjust arm_current_pl() for TrustZone Sergey Fedorov
2013-12-03 12:23 ` Peter Crosthwaite
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 09/21] target-arm: adjust SCR CP15 register access rights Sergey Fedorov
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 10/21] target-arm: add non-secure Translation Block flag Sergey Fedorov
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 11/21] target-arm: implement CPACR register logic Sergey Fedorov
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 12/21] target-arm: add NSACR support Sergey Fedorov
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 13/21] target-arm: add SDER definition Sergey Fedorov
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 14/21] target-arm: split TLB for secure state Sergey Fedorov
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 15/21] target-arm: add banked coprocessor register type Sergey Fedorov
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 16/21] target-arm: convert appropriate coprocessor registers to banked type Sergey Fedorov
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 17/21] target-arm: use c13_context field for CONTEXTIDR Sergey Fedorov
2013-12-19 4:31 ` Peter Crosthwaite
2013-12-19 6:29 ` Fedorov Sergey
2013-12-19 6:32 ` Peter Crosthwaite
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP registers Sergey Fedorov
2013-12-19 4:37 ` Peter Crosthwaite
2013-12-19 7:27 ` Fedorov Sergey
2013-12-19 11:38 ` Peter Maydell
2013-12-19 12:44 ` Peter Crosthwaite
2013-12-19 13:39 ` Fedorov Sergey
2013-12-19 14:01 ` Peter Crosthwaite
2013-12-19 14:09 ` Peter Maydell
2013-12-20 14:12 ` Fedorov Sergey
2013-12-20 14:33 ` Peter Maydell
2013-12-20 14:38 ` Fedorov Sergey
2013-12-20 16:18 ` Fedorov Sergey
2013-12-22 1:08 ` Peter Crosthwaite
2013-12-22 7:59 ` Peter Maydell
2013-12-23 7:28 ` Fedorov Sergey
2013-12-23 7:43 ` Fedorov Sergey
2013-12-23 9:05 ` Peter Maydell
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 19/21] target-arm: add MVBAR support Sergey Fedorov
2013-12-19 4:41 ` Peter Crosthwaite
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 20/21] target-arm: implement SMC instruction Sergey Fedorov
2013-12-03 8:48 ` [Qemu-devel] [RFC PATCH 21/21] target-arm: implement IRQ/FIQ routing to Monitor mode Sergey Fedorov
2013-12-04 10:08 ` [Qemu-devel] [RFC PATCH 00/21] target-arm: add CPU core TrustZone support Fedorov Sergey
2013-12-04 11:10 ` Peter Crosthwaite
2013-12-04 11:13 ` Peter Maydell
2013-12-04 12:48 ` Fedorov Sergey
2013-12-19 4:56 ` Peter Crosthwaite
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