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From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Laurent Desnogues" <laurent.desnogues@gmail.com>,
	"Patch Tracking" <patches@linaro.org>,
	"Michael Matz" <matz@suse.de>, "Alexander Graf" <agraf@suse.de>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"Claudio Fontana" <claudio.fontana@linaro.org>,
	"Dirk Mueller" <dmueller@suse.de>,
	"Will Newton" <will.newton@linaro.org>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>,
	"Christoffer Dall" <christoffer.dall@linaro.org>,
	"Richard Henderson" <rth@twiddle.net>
Subject: Re: [Qemu-devel] [PATCH 04/24] target-arm: Log bad system register accesses with LOG_UNIMP
Date: Sat, 25 Jan 2014 09:30:25 +1000	[thread overview]
Message-ID: <CAEgOgz6utnZHMwpWKRGCRUSCxTN22qOxr7s3Bjk4_+1QwB5Rmg@mail.gmail.com> (raw)
In-Reply-To: <1390335150-13470-5-git-send-email-peter.maydell@linaro.org>

On Wed, Jan 22, 2014 at 6:12 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> Log guest attempts to access unimplemented system registers via
> the LOG_UNIMP reporting mechanism (for both the 32 bit and 64 bit
> instruction sets). This is particularly useful for debugging
> problems where the guest is trying to use a system register that
> QEMU doesn't implement.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

> ---
>  target-arm/translate-a64.c |  7 ++++++-
>  target-arm/translate.c     | 13 +++++++++++++
>  2 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
> index a808a88..e0f6765 100644
> --- a/target-arm/translate-a64.c
> +++ b/target-arm/translate-a64.c
> @@ -1121,7 +1121,12 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
>                                                 crn, crm, op0, op1, op2));
>
>      if (!ri) {
> -        /* Unknown register */
> +        /* Unknown register; this might be a guest error or a QEMU
> +         * unimplemented feature.
> +         */
> +        qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 "
> +                      "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
> +                      isread ? "read" : "write", op0, op1, crn, crm, op2);
>          unallocated_encoding(s);
>          return;
>      }
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 8d240e1..59a206d 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -6672,6 +6672,19 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
>          return 0;
>      }
>
> +    /* Unknown register; this might be a guest error or a QEMU
> +     * unimplemented feature.
> +     */
> +    if (is64) {
> +        qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
> +                      "64 bit system register cp:%d opc1: %d crm:%d\n",
> +                      isread ? "read" : "write", cpnum, opc1, crm);
> +    } else {
> +        qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
> +                      "system register cp:%d opc1:%d crn:%d crm:%d opc2:%d\n",
> +                      isread ? "read" : "write", cpnum, opc1, crn, crm, opc2);
> +    }
> +
>      return 1;
>  }
>
> --
> 1.8.5
>
>

  reply	other threads:[~2014-01-24 23:30 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-01-21 20:12 [Qemu-devel] [PATCH 00/24] target-arm: implement some AArch64 system registers Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 01/24] target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs Peter Maydell
2014-01-23 12:04   ` Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 02/24] target-arm: Define names for SCTLR bits Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 03/24] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier Peter Maydell
2014-01-24 23:28   ` Peter Crosthwaite
2014-01-21 20:12 ` [Qemu-devel] [PATCH 04/24] target-arm: Log bad system register accesses with LOG_UNIMP Peter Maydell
2014-01-24 23:30   ` Peter Crosthwaite [this message]
2014-01-21 20:12 ` [Qemu-devel] [PATCH 05/24] target-arm: Add exception level to the AArch64 TB flags Peter Maydell
2014-01-28  1:28   ` Peter Crosthwaite
2014-01-28  8:42     ` Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 06/24] target-arm: A64: Implement store-exclusive for system mode Peter Maydell
2014-01-22  2:19   ` Hu Tao
2014-01-22 10:42     ` Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 07/24] target-arm: A64: Make cache ID registers visible to AArch64 Peter Maydell
2014-01-28  1:46   ` Peter Crosthwaite
2014-01-28  8:45     ` Peter Maydell
2014-01-28 14:05       ` Peter Crosthwaite
2014-01-28 18:12         ` Peter Maydell
2014-01-28 18:16           ` Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 08/24] target-arm: A64: Implement MSR (immediate) instructions Peter Maydell
2014-01-22  3:10   ` Hu Tao
2014-01-22 10:48     ` Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 09/24] target-arm: Implement AArch64 CurrentEL sysreg Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 10/24] target-arm: Implement AArch64 MIDR_EL1 Peter Maydell
2014-01-28  1:50   ` Peter Crosthwaite
2014-01-21 20:12 ` [Qemu-devel] [PATCH 11/24] target-arm: Implement AArch64 DAIF system register Peter Maydell
2014-01-28  1:54   ` Peter Crosthwaite
2014-01-28  8:46     ` Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 12/24] target-arm: Implement AArch64 cache invalidate/clean ops Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 13/24] target-arm: Implement AArch64 TLB invalidate ops Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 14/24] target-arm: Implement AArch64 dummy MDSCR_EL1 Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 15/24] target-arm: Implement AArch64 memory attribute registers Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 16/24] target-arm: Implement AArch64 SCTLR_EL1 Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 17/24] target-arm: Implement AArch64 TCR_EL1 Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 18/24] target-arm: Implement AArch64 VBAR_EL1 Peter Maydell
2014-01-25  0:11   ` Peter Crosthwaite
2014-01-21 20:12 ` [Qemu-devel] [PATCH 19/24] target-arm: Implement AArch64 TTBR* Peter Maydell
2014-01-24 23:44   ` Peter Crosthwaite
2014-01-25  0:09     ` Peter Maydell
2014-01-28  2:07       ` Peter Crosthwaite
2014-01-28  8:58         ` Peter Maydell
2014-01-28 11:42     ` Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 20/24] target-arm: Implement AArch64 MPIDR Peter Maydell
2014-01-25  0:12   ` Peter Crosthwaite
2014-01-21 20:12 ` [Qemu-devel] [PATCH 21/24] target-arm: Implement AArch64 generic timers Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 22/24] target-arm: Implement AArch64 ID and feature registers Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 23/24] target-arm: Implement AArch64 dummy breakpoint and watchpoint registers Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 24/24] target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI Peter Maydell

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