From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
To: Alistair Francis <alistair.francis@xilinx.com>
Cc: Edgar Iglesias <edgar.iglesias@xilinx.com>,
Peter Maydell <peter.maydell@linaro.org>,
zach.pfeffer@xilinx.com, Ryota Ozaki <ozaki.ryota@gmail.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"michals@xilinx.com" <michals@xilinx.com>
Subject: Re: [Qemu-devel] [PATCH target-arm v1 10/15] char: cadence_uart: Split state struct and type into header
Date: Mon, 2 Mar 2015 14:27:44 -0800 [thread overview]
Message-ID: <CAEgOgz7JRdpF==Tdap8af73Vs0zjqvW0_XdBg2HdHUGiXeU0rQ@mail.gmail.com> (raw)
In-Reply-To: <CAKmqyKM=GM5V6BkBXCBQWF6YmjShn1KutcMChVzHm0v3sUnOrQ@mail.gmail.com>
On Thu, Feb 26, 2015 at 7:26 PM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> On Tue, Feb 24, 2015 at 9:04 AM, Peter Crosthwaite
> <peter.crosthwaite@xilinx.com> wrote:
>> To allow using the device with modern SoC programming conventions. The
>> state struct needs to be visible to embed the device in SoC containers.
>>
>> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>> ---
>> hw/char/cadence_uart.c | 29 +----------------------------
>> include/hw/char/cadence_uart.h | 35 +++++++++++++++++++++++++++++++++++
>> 2 files changed, 36 insertions(+), 28 deletions(-)
>> create mode 100644 include/hw/char/cadence_uart.h
>>
>> diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
>> index 23f548d..4509e01 100644
>> --- a/hw/char/cadence_uart.c
>> +++ b/hw/char/cadence_uart.c
>> @@ -16,9 +16,7 @@
>> * with this program; if not, see <http://www.gnu.org/licenses/>.
>> */
>>
>> -#include "hw/sysbus.h"
>> -#include "sysemu/char.h"
>> -#include "qemu/timer.h"
>> +#include "hw/char/cadence_uart.h"
>>
>> #ifdef CADENCE_UART_ERR_DEBUG
>> #define DB_PRINT(...) do { \
>> @@ -85,8 +83,6 @@
>> #define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH)
>> #define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH)
>>
>> -#define CADENCE_UART_RX_FIFO_SIZE 16
>> -#define CADENCE_UART_TX_FIFO_SIZE 16
>> #define UART_INPUT_CLK 50000000
>>
>> #define R_CR (0x00/4)
>> @@ -108,29 +104,6 @@
>> #define R_PWID (0x40/4)
>> #define R_TTRIG (0x44/4)
>>
>> -#define CADENCE_UART_R_MAX (0x48/4)
>> -
>> -#define TYPE_CADENCE_UART "cadence_uart"
>> -#define CADENCE_UART(obj) OBJECT_CHECK(CadenceUARTState, (obj), \
>> - TYPE_CADENCE_UART)
>> -
>> -typedef struct {
>> - /*< private >*/
>> - SysBusDevice parent_obj;
>> - /*< public >*/
>> -
>> - MemoryRegion iomem;
>
> The same nit pick as the one I had for gem applies here as well.
> Although it is so minor.
>
Fixed
> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
>
Thanks,
Regards,
Peter
> Thanks,
>
> Alistair
>
>> - uint32_t r[CADENCE_UART_R_MAX];
>> - uint8_t rx_fifo[CADENCE_UART_RX_FIFO_SIZE];
>> - uint8_t tx_fifo[CADENCE_UART_TX_FIFO_SIZE];
>> - uint32_t rx_wpos;
>> - uint32_t rx_count;
>> - uint32_t tx_count;
>> - uint64_t char_tx_time;
>> - CharDriverState *chr;
>> - qemu_irq irq;
>> - QEMUTimer *fifo_trigger_handle;
>> -} CadenceUARTState;
>>
>> static void uart_update_status(CadenceUARTState *s)
>> {
>> diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h
>> new file mode 100644
>> index 0000000..0404785
>> --- /dev/null
>> +++ b/include/hw/char/cadence_uart.h
>> @@ -0,0 +1,35 @@
>> +#ifndef CADENCE_UART_H_
>> +
>> +#include "hw/sysbus.h"
>> +#include "sysemu/char.h"
>> +#include "qemu/timer.h"
>> +
>> +#define CADENCE_UART_RX_FIFO_SIZE 16
>> +#define CADENCE_UART_TX_FIFO_SIZE 16
>> +
>> +#define CADENCE_UART_R_MAX (0x48/4)
>> +
>> +#define TYPE_CADENCE_UART "cadence_uart"
>> +#define CADENCE_UART(obj) OBJECT_CHECK(CadenceUARTState, (obj), \
>> + TYPE_CADENCE_UART)
>> +
>> +typedef struct {
>> + /*< private >*/
>> + SysBusDevice parent_obj;
>> + /*< public >*/
>> +
>> + MemoryRegion iomem;
>> + uint32_t r[CADENCE_UART_R_MAX];
>> + uint8_t rx_fifo[CADENCE_UART_RX_FIFO_SIZE];
>> + uint8_t tx_fifo[CADENCE_UART_TX_FIFO_SIZE];
>> + uint32_t rx_wpos;
>> + uint32_t rx_count;
>> + uint32_t tx_count;
>> + uint64_t char_tx_time;
>> + CharDriverState *chr;
>> + qemu_irq irq;
>> + QEMUTimer *fifo_trigger_handle;
>> +} CadenceUARTState;
>> +
>> +#define CADENCE_UART_H_
>> +#endif
>> --
>> 2.3.0.1.g27a12f1
>>
>>
>
next prev parent reply other threads:[~2015-03-02 22:27 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-23 23:04 [Qemu-devel] [PATCH target-arm v1 00/15] Next Generation Xilinx Zynq SoC Peter Crosthwaite
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 01/15] target-arm: cpu64: Factor out ARM cortex init Peter Crosthwaite
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 02/15] target-arm: cpu64: Add support for cortex-a53 Peter Crosthwaite
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 03/15] arm: Introduce Xilinx Zynq MPSoC Peter Crosthwaite
2015-02-24 20:06 ` Michal Simek
2015-03-02 22:32 ` Peter Crosthwaite
2015-02-27 1:50 ` Alistair Francis
2015-03-02 20:08 ` Peter Crosthwaite
2015-03-02 22:31 ` Alistair Francis
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 04/15] arm: xlnx-zynq-mp: Add GIC Peter Crosthwaite
2015-02-27 1:59 ` Alistair Francis
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 05/15] arm: xlnx-zynq-mp: Connect CPU Timers to GIC Peter Crosthwaite
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 06/15] net: cadence_gem: Clean up variable names Peter Crosthwaite
2015-02-26 7:15 ` Alistair Francis
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 07/15] net: cadence_gem: Split state struct and type into header Peter Crosthwaite
2015-02-27 3:12 ` Alistair Francis
2015-03-02 22:24 ` Peter Crosthwaite
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 08/15] arm: xilinx-zynq-mp: Add GEM support Peter Crosthwaite
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 09/15] char: cadence_uart: Clean up variable names Peter Crosthwaite
2015-02-27 3:22 ` Alistair Francis
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 10/15] char: cadence_uart: Split state struct and type into header Peter Crosthwaite
2015-02-27 3:26 ` Alistair Francis
2015-03-02 22:27 ` Peter Crosthwaite [this message]
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 11/15] arm: xilinx-zynq-mp: Add UART support Peter Crosthwaite
2015-02-27 3:43 ` Alistair Francis
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 12/15] arm: Add xilinx-zynq-mp-generic machine Peter Crosthwaite
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 13/15] arm: xilinx-zynq-mp-generic: Add external RAM Peter Crosthwaite
2015-02-24 2:24 ` Alistair Francis
2015-03-02 19:40 ` Peter Crosthwaite
2015-03-02 22:38 ` Alistair Francis
2015-03-02 22:59 ` Peter Crosthwaite
2015-03-02 23:20 ` Alistair Francis
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 14/15] arm: xilinx-zynq-mp-generic: Add bootloading Peter Crosthwaite
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 15/15] arm: xlnx-zynq-mp: Add PSCI setup Peter Crosthwaite
2015-02-26 7:04 ` Alistair Francis
2015-03-02 19:56 ` Peter Crosthwaite
2015-02-27 3:38 ` [Qemu-devel] [PATCH target-arm v1 00/15] Next Generation Xilinx Zynq SoC Alistair Francis
2015-03-02 20:06 ` Peter Crosthwaite
2015-03-02 22:53 ` Alistair Francis
2015-03-02 23:05 ` Peter Crosthwaite
2015-03-02 23:22 ` Alistair Francis
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