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Date: Fri, 7 Jun 2013 14:19:06 +1000
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From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
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Subject: Re: [Qemu-devel] [PATCH] arm/zynq: Add software reset
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To: Sebastian Huber <sebastian.huber@embedded-brains.de>
Cc: qemu-devel@nongnu.org, git@xilinx.com

Hi Sebastian,

I'd like to get this merged with the fix I suggested. Are you able to
remake or ok if I ammend and resend your patch?

Regards,
Peter

On Tue, May 14, 2013 at 9:49 AM, Peter Crosthwaite
<peter.crosthwaite@xilinx.com> wrote:
> Hi Sebastian,
>
> Thanks for your contribution,
>
> On Wed, May 8, 2013 at 10:55 PM, Sebastian Huber
> <sebastian.huber@embedded-brains.de> wrote:
>> ---
>>  hw/misc/zynq_slcr.c |    3 +++
>>  1 files changed, 3 insertions(+), 0 deletions(-)
>>
>> diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
>> index 8418327..e88702e 100644
>> --- a/hw/misc/zynq_slcr.c
>> +++ b/hw/misc/zynq_slcr.c
>> @@ -396,6 +396,9 @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
>>                  goto bad_reg;
>>              }
>>              s->reset[(offset - 0x200) / 4] = val;
>> +            if (offset == 0x200 && val == 0x1) {
>
> The reset will only work if you have all the write-ignore bits in val
> cleared. Bit 0 is independent of those. It should read:
>
>             if (offset == 0x200 && val & 0x1) {
>
> To mask off all the don't care bits.
>
> Regards,
> Peter
>
>> +                qemu_system_reset_request();
>> +            }
>>              break;
>>          case 0x300:
>>              s->apu_ctrl = val;
>> --
>> 1.7.7
>>
>>