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X-Received-From: 2607:f8b0:4864:20::342 Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: Re: [Qemu-devel] [PATCH v2 13/28] riscv: sifive_e: prci: Update the PRCI register block size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , "qemu-devel@nongnu.org Developers" , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, Aug 7, 2019 at 3:49 PM Bin Meng wrote: > Currently the PRCI register block size is set to 0x8000, but in fact > 0x1000 is enough, which is also what the manual says. > > Signed-off-by: Bin Meng > --- > > Changes in v2: None > > hw/riscv/sifive_e_prci.c | 2 +- > include/hw/riscv/sifive_e_prci.h | 2 ++ > 2 files changed, 3 insertions(+), 1 deletion(-) > > diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c > index c906f11..4cbce48 100644 > --- a/hw/riscv/sifive_e_prci.c > +++ b/hw/riscv/sifive_e_prci.c > @@ -85,7 +85,7 @@ static void sifive_prci_init(Object *obj) > SiFivePRCIState *s = SIFIVE_E_PRCI(obj); > > memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s, > - TYPE_SIFIVE_E_PRCI, 0x8000); > + TYPE_SIFIVE_E_PRCI, SIFIVE_E_PRCI_REG_SIZE); > sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); > > s->hfrosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN); > diff --git a/include/hw/riscv/sifive_e_prci.h > b/include/hw/riscv/sifive_e_prci.h > index 7932fe7..81e506b 100644 > --- a/include/hw/riscv/sifive_e_prci.h > +++ b/include/hw/riscv/sifive_e_prci.h > @@ -47,6 +47,8 @@ enum { > SIFIVE_PRCI_PLLOUTDIV_DIV1 = (1 << 8) > }; > > +#define SIFIVE_E_PRCI_REG_SIZE 0x1000 > + > #define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci" > > #define SIFIVE_E_PRCI(obj) \ > -- > 2.7.4 > > > Reviewed-by: Chih-Min Chao