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From: Chih-Min Chao <chihmin.chao@sifive.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Richard Henderson <richard.henderson@linaro.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Ian Jiang <ianjiang.ict@gmail.com>
Subject: Re: [PATCH 3/6] target/riscv: Check for LEGAL NaN-boxing
Date: Tue, 30 Jun 2020 15:20:44 +0800	[thread overview]
Message-ID: <CAEiOBXWCVWhZ4oopTvmhU5yfSW+pdyJPDvqDfnvHD2DesXdAhQ@mail.gmail.com> (raw)
In-Reply-To: <20200626205917.4545-4-zhiwei_liu@c-sky.com>

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On Sat, Jun 27, 2020 at 5:05 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:

> A narrow n-bit operation, where n < FLEN, checks that input operands
> are correctly NaN-boxed, i.e., all upper FLEN - n bits are 1.
> If so, the n least-significant bits of the input are used as the input
> value,
> otherwise the input value is treated as an n-bit canonical NaN.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
>  target/riscv/translate.c | 29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 4b1534c9a6..1c9b809d4a 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -104,6 +104,35 @@ static void gen_nanbox_fpr(DisasContext *ctx, int
> regno)
>      }
>  }
>
> +/*
> + * A narrow n-bit operation, where n < FLEN, checks that input operands
> + * are correctly NaN-boxed, i.e., all upper FLEN - n bits are 1.
> + * If so, the n least-signicant bits of the input are used as the input
> value,
> + * otherwise the input value is treated as an n-bit canonical NaN.
> + * (riscv-spec-v2.2 Section 9.2).
> + */
> +static void check_nanboxed(DisasContext *ctx, int num, ...)
> +{
> +    if (has_ext(ctx, RVD)) {
> +        int i;
> +        TCGv_i64 cond1 = tcg_temp_new_i64();
>
forget to remove ?

> +        TCGv_i64 t_nan = tcg_const_i64(0x7fc00000);
> +        TCGv_i64 t_max = tcg_const_i64(MAKE_64BIT_MASK(32, 32));
> +        va_list valist;
> +        va_start(valist, num);
> +
> +        for (i = 0; i < num; i++) {
> +            TCGv_i64 t = va_arg(valist, TCGv_i64);
> +            tcg_gen_movcond_i64(TCG_COND_GEU, t, t, t_max, t, t_nan);
> +        }
> +
> +        va_end(valist);
> +        tcg_temp_free_i64(cond1);
>
forget to remove ?

> +        tcg_temp_free_i64(t_nan);
> +        tcg_temp_free_i64(t_max);
> +    }
> +}
> +
>  static void generate_exception(DisasContext *ctx, int excp)
>  {
>      tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
> --
> 2.23.0
>
>

 Chih-Min Chao

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  reply	other threads:[~2020-06-30  7:21 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-26 20:59 [PATCH 0/6] target/riscv: NaN-boxing for multiple precison LIU Zhiwei
2020-06-26 20:59 ` [PATCH 1/6] target/riscv: move gen_nanbox_fpr to translate.c LIU Zhiwei
2020-07-02 17:13   ` Richard Henderson
2020-06-26 20:59 ` [PATCH 2/6] target/riscv: NaN-boxing compute, sign-injection and convert instructions LIU Zhiwei
2020-07-02 17:15   ` Richard Henderson
2020-06-26 20:59 ` [PATCH 3/6] target/riscv: Check for LEGAL NaN-boxing LIU Zhiwei
2020-06-30  7:20   ` Chih-Min Chao [this message]
2020-06-30  7:31     ` LIU Zhiwei
2020-06-26 20:59 ` [PATCH 4/6] target/riscv: check before allocating TCG temps LIU Zhiwei
2020-07-02 17:13   ` Richard Henderson
2020-06-26 20:59 ` [PATCH 5/6] target/riscv: Flush not valid NaN-boxing input to canonical NaN LIU Zhiwei
2020-06-30  7:31   ` Chih-Min Chao
2020-06-30  7:37     ` LIU Zhiwei
2020-07-02  6:29       ` Chih-Min Chao
2020-06-26 20:59 ` [PATCH 6/6] target/riscv: clean up fmv.w.x LIU Zhiwei
2020-07-02 17:38   ` Richard Henderson
2020-06-26 21:21 ` [PATCH 0/6] target/riscv: NaN-boxing for multiple precison no-reply
2020-07-02 17:37 ` Richard Henderson
     [not found]   ` <3c139607-9cac-a28a-c296-b0e147b3b20f@c-sky.com>
2020-07-07 21:45     ` LIU Zhiwei
2020-07-08 15:35       ` Richard Henderson
2020-07-10  7:03         ` LIU Zhiwei
2020-07-10 16:03           ` Richard Henderson

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