From: Chih-Min Chao <chihmin.chao@sifive.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: Frank Chang <frank.chang@sifive.com>,
Alistair Francis <alistair23@gmail.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
liuzhiwei <zhiwei_liu@c-sky.com>
Subject: Re: [PATCH v2 4/7] target/riscv: Check nanboxed inputs to fp helpers
Date: Thu, 6 Aug 2020 14:26:17 +0800 [thread overview]
Message-ID: <CAEiOBXWs44cpuVC+vKtK612f3vKveh5e37aO42xOnkVoq67r-A@mail.gmail.com> (raw)
In-Reply-To: <20200724002807.441147-5-richard.henderson@linaro.org>
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On Fri, Jul 24, 2020 at 8:29 AM Richard Henderson <
richard.henderson@linaro.org> wrote:
> If a 32-bit input is not properly nanboxed, then the input is
> replaced with the default qnan.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/riscv/internals.h | 11 +++++++
> target/riscv/fpu_helper.c | 64 ++++++++++++++++++++++++++++-----------
> 2 files changed, 57 insertions(+), 18 deletions(-)
>
> diff --git a/target/riscv/internals.h b/target/riscv/internals.h
> index 9f4ba7d617..f1a546dba6 100644
> --- a/target/riscv/internals.h
> +++ b/target/riscv/internals.h
> @@ -43,4 +43,15 @@ static inline uint64_t nanbox_s(float32 f)
> return f | MAKE_64BIT_MASK(32, 32);
> }
>
> +static inline float32 check_nanbox_s(uint64_t f)
> +{
> + uint64_t mask = MAKE_64BIT_MASK(32, 32);
> +
> + if (likely((f & mask) == mask)) {
> + return (uint32_t)f;
> + } else {
> + return 0x7fc00000u; /* default qnan */
> + }
> +}
> +
> #endif
> diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
> index 72541958a7..bb346a8249 100644
> --- a/target/riscv/fpu_helper.c
> +++ b/target/riscv/fpu_helper.c
> @@ -81,9 +81,12 @@ void helper_set_rounding_mode(CPURISCVState *env,
> uint32_t rm)
> set_float_rounding_mode(softrm, &env->fp_status);
> }
>
> -static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t
> frs2,
> - uint64_t frs3, int flags)
> +static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2,
> + uint64_t rs3, int flags)
> {
> + float32 frs1 = check_nanbox_s(rs1);
> + float32 frs2 = check_nanbox_s(rs2);
> + float32 frs3 = check_nanbox_s(rs3);
> return nanbox_s(float32_muladd(frs1, frs2, frs3, flags,
> &env->fp_status));
> }
>
> @@ -139,74 +142,97 @@ uint64_t helper_fnmadd_d(CPURISCVState *env,
> uint64_t frs1, uint64_t frs2,
> float_muladd_negate_product, &env->fp_status);
> }
>
> -uint64_t helper_fadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
> +uint64_t helper_fadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
> {
> + float32 frs1 = check_nanbox_s(rs1);
> + float32 frs2 = check_nanbox_s(rs2);
> return nanbox_s(float32_add(frs1, frs2, &env->fp_status));
> }
>
> -uint64_t helper_fsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
> +uint64_t helper_fsub_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
> {
> + float32 frs1 = check_nanbox_s(rs1);
> + float32 frs2 = check_nanbox_s(rs2);
> return nanbox_s(float32_sub(frs1, frs2, &env->fp_status));
> }
>
> -uint64_t helper_fmul_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
> +uint64_t helper_fmul_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
> {
> + float32 frs1 = check_nanbox_s(rs1);
> + float32 frs2 = check_nanbox_s(rs2);
> return nanbox_s(float32_mul(frs1, frs2, &env->fp_status));
> }
>
> -uint64_t helper_fdiv_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
> +uint64_t helper_fdiv_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
> {
> + float32 frs1 = check_nanbox_s(rs1);
> + float32 frs2 = check_nanbox_s(rs2);
> return nanbox_s(float32_div(frs1, frs2, &env->fp_status));
> }
>
> -uint64_t helper_fmin_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
> +uint64_t helper_fmin_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
> {
> + float32 frs1 = check_nanbox_s(rs1);
> + float32 frs2 = check_nanbox_s(rs2);
> return nanbox_s(float32_minnum(frs1, frs2, &env->fp_status));
> }
>
> -uint64_t helper_fmax_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
> +uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
> {
> + float32 frs1 = check_nanbox_s(rs1);
> + float32 frs2 = check_nanbox_s(rs2);
> return nanbox_s(float32_maxnum(frs1, frs2, &env->fp_status));
> }
>
> -uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t frs1)
> +uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1)
> {
> + float32 frs1 = check_nanbox_s(rs1);
> return nanbox_s(float32_sqrt(frs1, &env->fp_status));
> }
>
> -target_ulong helper_fle_s(CPURISCVState *env, uint64_t frs1, uint64_t
> frs2)
> +target_ulong helper_fle_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
> {
> + float32 frs1 = check_nanbox_s(rs1);
> + float32 frs2 = check_nanbox_s(rs2);
> return float32_le(frs1, frs2, &env->fp_status);
> }
>
> -target_ulong helper_flt_s(CPURISCVState *env, uint64_t frs1, uint64_t
> frs2)
> +target_ulong helper_flt_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
> {
> + float32 frs1 = check_nanbox_s(rs1);
> + float32 frs2 = check_nanbox_s(rs2);
> return float32_lt(frs1, frs2, &env->fp_status);
> }
>
> -target_ulong helper_feq_s(CPURISCVState *env, uint64_t frs1, uint64_t
> frs2)
> +target_ulong helper_feq_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
> {
> + float32 frs1 = check_nanbox_s(rs1);
> + float32 frs2 = check_nanbox_s(rs2);
> return float32_eq_quiet(frs1, frs2, &env->fp_status);
> }
>
> -target_ulong helper_fcvt_w_s(CPURISCVState *env, uint64_t frs1)
> +target_ulong helper_fcvt_w_s(CPURISCVState *env, uint64_t rs1)
> {
> + float32 frs1 = check_nanbox_s(rs1);
> return float32_to_int32(frs1, &env->fp_status);
> }
>
> -target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t frs1)
> +target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t rs1)
> {
> + float32 frs1 = check_nanbox_s(rs1);
> return (int32_t)float32_to_uint32(frs1, &env->fp_status);
> }
>
> #if defined(TARGET_RISCV64)
> -uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t frs1)
> +uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
> {
> + float32 frs1 = check_nanbox_s(rs1);
> return float32_to_int64(frs1, &env->fp_status);
> }
>
> -uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t frs1)
> +uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
> {
> + float32 frs1 = check_nanbox_s(rs1);
> return float32_to_uint64(frs1, &env->fp_status);
> }
> #endif
> @@ -233,8 +259,9 @@ uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t
> rs1)
> }
> #endif
>
> -target_ulong helper_fclass_s(uint64_t frs1)
> +target_ulong helper_fclass_s(uint64_t rs1)
> {
> + float32 frs1 = check_nanbox_s(rs1);
> return fclass_s(frs1);
> }
>
> @@ -275,7 +302,8 @@ uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t
> rs1)
>
> uint64_t helper_fcvt_d_s(CPURISCVState *env, uint64_t rs1)
> {
> - return float32_to_float64(rs1, &env->fp_status);
> + float32 frs1 = check_nanbox_s(rs1);
> + return float32_to_float64(frs1, &env->fp_status);
> }
>
> uint64_t helper_fsqrt_d(CPURISCVState *env, uint64_t frs1)
> --
> 2.25.1
>
>
>
Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>
Chih-Min Chao
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next prev parent reply other threads:[~2020-08-06 11:59 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-24 0:28 [PATCH v2 0/7] target/riscv: NaN-boxing for multiple precison Richard Henderson
2020-07-24 0:28 ` [PATCH v2 1/7] target/riscv: Generate nanboxed results from fp helpers Richard Henderson
2020-07-24 2:35 ` LIU Zhiwei
2020-07-24 3:55 ` Richard Henderson
2020-07-24 6:05 ` LIU Zhiwei
2020-08-06 6:09 ` Chih-Min Chao
2020-08-06 7:05 ` LIU Zhiwei
2020-08-06 8:42 ` Chih-Min Chao
2020-08-06 10:02 ` LIU Zhiwei
2020-07-24 0:28 ` [PATCH v2 2/7] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s Richard Henderson
2020-07-24 2:39 ` LIU Zhiwei
2020-08-06 6:24 ` Chih-Min Chao
2020-07-24 0:28 ` [PATCH v2 3/7] target/riscv: Generate nanboxed results from trans_rvf.inc.c Richard Henderson
2020-07-24 2:41 ` LIU Zhiwei
2020-08-06 6:24 ` Chih-Min Chao
2020-07-24 0:28 ` [PATCH v2 4/7] target/riscv: Check nanboxed inputs to fp helpers Richard Henderson
2020-07-24 2:47 ` LIU Zhiwei
2020-07-24 3:59 ` Richard Henderson
2020-08-06 6:26 ` Chih-Min Chao [this message]
2020-07-24 0:28 ` [PATCH v2 5/7] target/riscv: Check nanboxed inputs in trans_rvf.inc.c Richard Henderson
2020-07-24 6:04 ` LIU Zhiwei
2020-08-06 6:27 ` Chih-Min Chao
2020-08-07 20:24 ` Chih-Min Chao
2020-08-08 14:18 ` LIU Zhiwei
2020-08-08 23:06 ` LIU Zhiwei
2020-07-24 0:28 ` [PATCH v2 6/7] target/riscv: Clean up fmv.w.x Richard Henderson
2020-08-06 6:28 ` Chih-Min Chao
2020-07-24 0:28 ` [PATCH v2 7/7] target/riscv: check before allocating TCG temps Richard Henderson
2020-08-06 6:28 ` Chih-Min Chao
2020-07-24 2:31 ` [PATCH v2 0/7] target/riscv: NaN-boxing for multiple precison LIU Zhiwei
2020-07-27 23:37 ` Alistair Francis
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