From: Chih-Min Chao <chihmin.chao@sifive.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
palmer@dabbelt.com, Ian Jiang <ianjiang.ict@gmail.com>
Subject: Re: [PATCH v2] riscv: Add helper to make NaN-boxing for FP register
Date: Tue, 9 Jun 2020 18:07:30 +0800 [thread overview]
Message-ID: <CAEiOBXXOA40F5kdttMby6eAfMGYVT0twZOhkojFK9qRDX1Xchw@mail.gmail.com> (raw)
In-Reply-To: <b14a65dd-b565-77ca-d479-f88e53ca0721@linaro.org>
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ping ? Could this be merged ?
Chih-Min Chao
On Wed, Jan 29, 2020 at 3:43 AM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 1/27/20 4:37 PM, Ian Jiang wrote:
> > The function that makes NaN-boxing when a 32-bit value is assigned
> > to a 64-bit FP register is split out to a helper gen_nanbox_fpr().
> > Then it is applied in translating of the FLW instruction.
> >
> > Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
> > ---
> > target/riscv/insn_trans/trans_rvf.inc.c | 17 +++++++++++++++--
> > 1 file changed, 15 insertions(+), 2 deletions(-)
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
>
> r~
>
>
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next prev parent reply other threads:[~2020-06-09 10:08 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-28 0:37 [PATCH v2] riscv: Add helper to make NaN-boxing for FP register Ian Jiang
2020-01-28 0:41 ` Alistair Francis
2020-01-28 18:32 ` Richard Henderson
2020-06-09 10:07 ` Chih-Min Chao [this message]
2020-06-09 23:16 ` Alistair Francis
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