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Wed, 03 Dec 2025 15:34:39 -0800 (PST) X-Google-Smtp-Source: AGHT+IHd05vlVQ89zVwnMSiT3JcT9g+NYmmcsuee+l8Wm2zct/c4iU8Q1KGWnRZndGk9a/CQ3OvNB66EhopMJ0RvF9U= X-Received: by 2002:a05:690e:d81:b0:63f:a18d:e151 with SMTP id 956f58d0204a3-6443d909d31mr972931d50.35.1764804878933; Wed, 03 Dec 2025 15:34:38 -0800 (PST) MIME-Version: 1.0 References: <20251114230013.158098-1-ltaylorsimpson@gmail.com> <20251114230013.158098-2-ltaylorsimpson@gmail.com> In-Reply-To: <20251114230013.158098-2-ltaylorsimpson@gmail.com> From: Brian Cain Date: Wed, 3 Dec 2025 17:34:26 -0600 X-Gm-Features: AWmQ_bl9dJ_EzSDbm2DK76j9ju20SYHFyw400xL0nRSlDxdGGH-fihKolEQDVgM Message-ID: Subject: Re: [PATCH 1/4] Hexagon (target/hexagon) Remove gen_log_reg_write To: Taylor Simpson Cc: qemu-devel@nongnu.org, matheus.bernardino@oss.qualcomm.com, sid.manning@oss.qualcomm.com, marco.liebel@oss.qualcomm.com, richard.henderson@linaro.org, philmd@linaro.org, ale@rev.ng, anjo@rev.ng Content-Type: multipart/alternative; boundary="000000000000e82ca2064514a717" X-Authority-Analysis: v=2.4 cv=GMMF0+NK c=1 sm=1 tr=0 ts=6930c911 cx=c_pps a=J+5FMm3BkXb42VdG8aMU9w==:117 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=pGLkceISAAAA:8 a=EUspDBNiAAAA:8 a=S25X5_Vwpc312vOpBhkA:9 a=QEXdDO2ut3YA:10 a=xUQTeEI1AAAA:8 a=YdTJNS3KMcMpdLE9gUMA:9 a=cj0BF4Z9l-ad4Aca:21 a=lqcHg5cX4UMA:10 a=Epx66wHExT0cjJnnR-oj:22 a=n63FNrGa8kYyhQnjR337:22 X-Proofpoint-ORIG-GUID: MJZtF6KqxZINXkjP-OSSHDxe8GTbzXhO X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjAzMDE4NyBTYWx0ZWRfX3VdWY3x6ab1V f/ZzqwJyMBtEVHR/0gsQrnGg5r5wCOePmdTRB+iMUzMkxiu+rlwaL90BruopDWpnNNLgrmuMYeM JwWvpohRbg442zmWusBK+UvJ8Xrqdjzpw+qQyR9cwTAbXIrWRMg0CC0iVQtW8GCpC+gaUsahxHG RtsTNlMeOdNOwSkklOb6dXNlm4I4vA/EWLpEddObmLOgU7TzOu0RD89kjYi4a3nmGZBckrRt4pS F+dlz5dvbM9xHC41maHS2fBopzWIS6gFD1kpj6XvqfHJQtsh+YEs8hkflJz4Aed2aL2+NhS8RgN lcG+5W+iz26NylbR0KcBQiWcRvU29Ky/S+EyGTnMIghaxGqqf5uyGaSyruoqKT5NdRYkX81+EZ1 yrEzIP/t+c0l4LgQR8GX5rvfyhrZVw== X-Proofpoint-GUID: MJZtF6KqxZINXkjP-OSSHDxe8GTbzXhO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-03_03,2025-12-03_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 malwarescore=0 spamscore=0 bulkscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512030187 Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_BL_SPAMCOP_NET=1.347, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --000000000000e82ca2064514a717 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, Nov 14, 2025 at 5:00=E2=80=AFPM Taylor Simpson wrote: > The gen_log_reg_write function is a memnant of the original Hexagon > target design. With the addition of gen_analyze_funcs.py and the > ability to short-circuit a packet commit, this function can be > removed. > > Note that the implementation of gen_log_reg_write contains a check > of the register mutability mask. This is only needed for control > registers, so we move it to gen_write_ctrl_reg. > > We do need the gen_log_reg_write_pair function, but the name is > now misleading, so we change the name go gen_write_reg_pair. > > Signed-off-by: Taylor Simpson > --- > Reviewed-by: Brian Cain > target/hexagon/gen_tcg.h | 7 +-- > target/hexagon/genptr.h | 1 - > target/hexagon/genptr.c | 64 ++++++++------------- > target/hexagon/idef-parser/parser-helpers.c | 2 +- > target/hexagon/README | 10 ++-- > target/hexagon/gen_tcg_funcs.py | 1 - > target/hexagon/hex_common.py | 14 ++--- > 7 files changed, 40 insertions(+), 59 deletions(-) > > diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h > index 8a3b801287..10123336b1 100644 > --- a/target/hexagon/gen_tcg.h > +++ b/target/hexagon/gen_tcg.h > @@ -509,10 +509,9 @@ > /* sub-instruction version (no RxV, so handle it manually) */ > #define fGEN_TCG_SS2_allocframe(SHORTCODE) \ > do { \ > - TCGv r29 =3D tcg_temp_new(); \ > + TCGv r29 =3D get_result_gpr(ctx, HEX_REG_SP); \ > tcg_gen_mov_tl(r29, hex_gpr[HEX_REG_SP]); \ > gen_allocframe(ctx, r29, uiV); \ > - gen_log_reg_write(ctx, HEX_REG_SP, r29); \ > } while (0) > > /* > @@ -528,7 +527,7 @@ > do { \ > TCGv_i64 r31_30 =3D tcg_temp_new_i64(); \ > gen_deallocframe(ctx, r31_30, hex_gpr[HEX_REG_FP]); \ > - gen_log_reg_write_pair(ctx, HEX_REG_FP, r31_30); \ > + gen_write_reg_pair(ctx, HEX_REG_FP, r31_30); \ > } while (0) > > /* > @@ -546,7 +545,7 @@ > do { \ > TCGv_i64 RddV =3D get_result_gpr_pair(ctx, HEX_REG_FP); \ > gen_return(ctx, RddV, hex_gpr[HEX_REG_FP]); \ > - gen_log_reg_write_pair(ctx, HEX_REG_FP, RddV); \ > + gen_write_reg_pair(ctx, HEX_REG_FP, RddV); \ > } while (0) > > /* > diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h > index a4b43c2910..d932255042 100644 > --- a/target/hexagon/genptr.h > +++ b/target/hexagon/genptr.h > @@ -37,7 +37,6 @@ TCGv gen_read_reg(TCGv result, int num); > TCGv gen_read_preg(TCGv pred, uint8_t num); > TCGv get_result_gpr(DisasContext *ctx, int rnum); > TCGv get_result_pred(DisasContext *ctx, int pnum); > -void gen_log_reg_write(DisasContext *ctx, int rnum, TCGv val); > void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val); > void gen_set_usr_field(DisasContext *ctx, int field, TCGv val); > void gen_set_usr_fieldi(DisasContext *ctx, int field, int x); > diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c > index cecaece4ae..e58021ed6c 100644 > --- a/target/hexagon/genptr.c > +++ b/target/hexagon/genptr.c > @@ -94,25 +94,17 @@ static TCGv_i64 get_result_gpr_pair(DisasContext *ctx= , > int rnum) > return result; > } > > -void gen_log_reg_write(DisasContext *ctx, int rnum, TCGv val) > -{ > - const target_ulong reg_mask =3D reg_immut_masks[rnum]; > - > - gen_masked_reg_write(val, hex_gpr[rnum], reg_mask); > - tcg_gen_mov_tl(get_result_gpr(ctx, rnum), val); > -} > - > -static void gen_log_reg_write_pair(DisasContext *ctx, int rnum, TCGv_i64 > val) > +static void gen_write_reg_pair(DisasContext *ctx, int rnum, TCGv_i64 val= ) > { > TCGv val32 =3D tcg_temp_new(); > > /* Low word */ > tcg_gen_extrl_i64_i32(val32, val); > - gen_log_reg_write(ctx, rnum, val32); > + tcg_gen_mov_tl(get_result_gpr(ctx, rnum), val32); > > /* High word */ > tcg_gen_extrh_i64_i32(val32, val); > - gen_log_reg_write(ctx, rnum + 1, val32); > + tcg_gen_mov_tl(get_result_gpr(ctx, rnum + 1), val32); > } > > TCGv get_result_pred(DisasContext *ctx, int pnum) > @@ -240,7 +232,9 @@ static inline void gen_write_ctrl_reg(DisasContext > *ctx, int reg_num, > if (reg_num =3D=3D HEX_REG_P3_0_ALIASED) { > gen_write_p3_0(ctx, val); > } else { > - gen_log_reg_write(ctx, reg_num, val); > + const target_ulong reg_mask =3D reg_immut_masks[reg_num]; > + gen_masked_reg_write(val, hex_gpr[reg_num], reg_mask); > + tcg_gen_mov_tl(get_result_gpr(ctx, reg_num), val); > if (reg_num =3D=3D HEX_REG_QEMU_PKT_CNT) { > ctx->num_packets =3D 0; > } > @@ -256,23 +250,15 @@ static inline void gen_write_ctrl_reg(DisasContext > *ctx, int reg_num, > static inline void gen_write_ctrl_reg_pair(DisasContext *ctx, int reg_nu= m, > TCGv_i64 val) > { > - if (reg_num =3D=3D HEX_REG_P3_0_ALIASED) { > - TCGv result =3D get_result_gpr(ctx, reg_num + 1); > - TCGv val32 =3D tcg_temp_new(); > - tcg_gen_extrl_i64_i32(val32, val); > - gen_write_p3_0(ctx, val32); > - tcg_gen_extrh_i64_i32(val32, val); > - tcg_gen_mov_tl(result, val32); > - } else { > - gen_log_reg_write_pair(ctx, reg_num, val); > - if (reg_num =3D=3D HEX_REG_QEMU_PKT_CNT) { > - ctx->num_packets =3D 0; > - ctx->num_insns =3D 0; > - } > - if (reg_num =3D=3D HEX_REG_QEMU_HVX_CNT) { > - ctx->num_hvx_insns =3D 0; > - } > - } > + TCGv val32 =3D tcg_temp_new(); > + > + /* Low word */ > + tcg_gen_extrl_i64_i32(val32, val); > + gen_write_ctrl_reg(ctx, reg_num, val32); > + > + /* High word */ > + tcg_gen_extrh_i64_i32(val32, val); > + gen_write_ctrl_reg(ctx, reg_num + 1, val32); > } > > TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign) > @@ -541,8 +527,8 @@ static inline void gen_loop0r(DisasContext *ctx, TCGv > RsV, int riV) > { > fIMMEXT(riV); > fPCALIGN(riV); > - gen_log_reg_write(ctx, HEX_REG_LC0, RsV); > - gen_log_reg_write(ctx, HEX_REG_SA0, tcg_constant_tl(ctx->pkt->pc + > riV)); > + tcg_gen_mov_tl(get_result_gpr(ctx, HEX_REG_LC0), RsV); > + tcg_gen_movi_tl(get_result_gpr(ctx, HEX_REG_SA0), ctx->pkt->pc + riV= ); > gen_set_usr_fieldi(ctx, USR_LPCFG, 0); > } > > @@ -555,8 +541,8 @@ static inline void gen_loop1r(DisasContext *ctx, TCGv > RsV, int riV) > { > fIMMEXT(riV); > fPCALIGN(riV); > - gen_log_reg_write(ctx, HEX_REG_LC1, RsV); > - gen_log_reg_write(ctx, HEX_REG_SA1, tcg_constant_tl(ctx->pkt->pc + > riV)); > + tcg_gen_mov_tl(get_result_gpr(ctx, HEX_REG_LC1), RsV); > + tcg_gen_movi_tl(get_result_gpr(ctx, HEX_REG_SA1), ctx->pkt->pc + riV= ); > } > > static void gen_loop1i(DisasContext *ctx, int count, int riV) > @@ -568,8 +554,8 @@ static void gen_ploopNsr(DisasContext *ctx, int N, > TCGv RsV, int riV) > { > fIMMEXT(riV); > fPCALIGN(riV); > - gen_log_reg_write(ctx, HEX_REG_LC0, RsV); > - gen_log_reg_write(ctx, HEX_REG_SA0, tcg_constant_tl(ctx->pkt->pc + > riV)); > + tcg_gen_mov_tl(get_result_gpr(ctx, HEX_REG_LC0), RsV); > + tcg_gen_movi_tl(get_result_gpr(ctx, HEX_REG_SA0), ctx->pkt->pc + riV= ); > gen_set_usr_fieldi(ctx, USR_LPCFG, N); > gen_log_pred_write(ctx, 3, tcg_constant_tl(0)); > } > @@ -773,25 +759,23 @@ static void gen_framecheck(TCGv EA, int framesize) > > static void gen_allocframe(DisasContext *ctx, TCGv r29, int framesize) > { > - TCGv r30 =3D tcg_temp_new(); > + TCGv r30 =3D get_result_gpr(ctx, HEX_REG_FP); > TCGv_i64 frame; > tcg_gen_addi_tl(r30, r29, -8); > frame =3D gen_frame_scramble(); > gen_store8(tcg_env, r30, frame, ctx->insn->slot); > - gen_log_reg_write(ctx, HEX_REG_FP, r30); > gen_framecheck(r30, framesize); > tcg_gen_subi_tl(r29, r30, framesize); > } > > static void gen_deallocframe(DisasContext *ctx, TCGv_i64 r31_30, TCGv r3= 0) > { > - TCGv r29 =3D tcg_temp_new(); > + TCGv r29 =3D get_result_gpr(ctx, HEX_REG_SP); > TCGv_i64 frame =3D tcg_temp_new_i64(); > gen_load_frame(ctx, frame, r30); > gen_frame_unscramble(frame); > tcg_gen_mov_i64(r31_30, frame); > tcg_gen_addi_tl(r29, r30, 8); > - gen_log_reg_write(ctx, HEX_REG_SP, r29); > } > #endif > > @@ -833,7 +817,7 @@ static void gen_cond_return_subinsn(DisasContext *ctx= , > TCGCond cond, TCGv pred) > { > TCGv_i64 RddV =3D get_result_gpr_pair(ctx, HEX_REG_FP); > gen_cond_return(ctx, RddV, hex_gpr[HEX_REG_FP], pred, cond); > - gen_log_reg_write_pair(ctx, HEX_REG_FP, RddV); > + gen_write_reg_pair(ctx, HEX_REG_FP, RddV); > } > > static void gen_endloop0(DisasContext *ctx) > diff --git a/target/hexagon/idef-parser/parser-helpers.c > b/target/hexagon/idef-parser/parser-helpers.c > index 1dc52b4e02..f5802ceadb 100644 > --- a/target/hexagon/idef-parser/parser-helpers.c > +++ b/target/hexagon/idef-parser/parser-helpers.c > @@ -1315,7 +1315,7 @@ void gen_write_reg(Context *c, YYLTYPE *locp, > HexValue *reg, HexValue *value) > value_m =3D rvalue_materialize(c, locp, &value_m); > OUT(c, > locp, > - "gen_log_reg_write(ctx, ", ®->reg.id, ", ", > + "tcg_gen_mov_tl(get_result_gpr(ctx, ", ®->reg.id, "), ", > &value_m, ");\n"); > } > > diff --git a/target/hexagon/README b/target/hexagon/README > index ca617e3364..1938c91af8 100644 > --- a/target/hexagon/README > +++ b/target/hexagon/README > @@ -80,12 +80,14 @@ tcg_funcs_generated.c.inc > Insn *insn, > Packet *pkt) > { > - TCGv RdV =3D tcg_temp_new(); > + Insn *insn G_GNUC_UNUSED =3D ctx->insn; > const int RdN =3D insn->regno[0]; > - TCGv RsV =3D hex_gpr[insn->regno[1]]; > - TCGv RtV =3D hex_gpr[insn->regno[2]]; > + TCGv RdV =3D get_result_gpr(ctx, RdN); > + const int RsN =3D insn->regno[1]; > + TCGv RsV =3D hex_gpr[RsN]; > + const int RtN =3D insn->regno[2]; > + TCGv RtV =3D hex_gpr[RtN]; > gen_helper_A2_add(RdV, tcg_env, RsV, RtV); > - gen_log_reg_write(ctx, RdN, RdV); > } > > helper_funcs_generated.c.inc > diff --git a/target/hexagon/gen_tcg_funcs.py > b/target/hexagon/gen_tcg_funcs.py > index c2ba91ddc0..bd241afde1 100755 > --- a/target/hexagon/gen_tcg_funcs.py > +++ b/target/hexagon/gen_tcg_funcs.py > @@ -35,7 +35,6 @@ > ## TCGv RsV =3D hex_gpr[insn->regno[1]]; > ## TCGv RtV =3D hex_gpr[insn->regno[2]]; > ## > -## gen_log_reg_write(ctx, RdN, RdV); > ## } > ## > ## where depends on hex_common.skip_qemu_helper(tag) > diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py > index 6803908718..093def9386 100755 > --- a/target/hexagon/hex_common.py > +++ b/target/hexagon/hex_common.py > @@ -452,9 +452,8 @@ def decl_tcg(self, f, tag, regno): > TCGv {self.reg_tcg()} =3D get_result_gpr(ctx, {self.reg_num}= ); > """)) > def log_write(self, f, tag): > - f.write(code_fmt(f"""\ > - gen_log_reg_write(ctx, {self.reg_num}, {self.reg_tcg()}); > - """)) > + ## No write needed > + return > def analyze_write(self, f, tag, regno): > predicated =3D "true" if is_predicated(tag) else "false" > f.write(code_fmt(f"""\ > @@ -496,9 +495,8 @@ def decl_tcg(self, f, tag, regno): > tcg_gen_mov_tl({self.reg_tcg()}, hex_gpr[{self.reg_num}]= ); > """)) > def log_write(self, f, tag): > - f.write(code_fmt(f"""\ > - gen_log_reg_write(ctx, {self.reg_num}, {self.reg_tcg()}); > - """)) > + ## No write needed > + return > def analyze_read(self, f, regno): > f.write(code_fmt(f"""\ > ctx_log_reg_read(ctx, {self.reg_num}); > @@ -630,7 +628,7 @@ def decl_tcg(self, f, tag, regno): > """)) > def log_write(self, f, tag): > f.write(code_fmt(f"""\ > - gen_log_reg_write_pair(ctx, {self.reg_num}, {self.reg_tcg()}= ); > + gen_write_reg_pair(ctx, {self.reg_num}, {self.reg_tcg()}); > """)) > def analyze_write(self, f, tag, regno): > predicated =3D "true" if is_predicated(tag) else "false" > @@ -664,7 +662,7 @@ def decl_tcg(self, f, tag, regno): > """)) > def log_write(self, f, tag): > f.write(code_fmt(f"""\ > - gen_log_reg_write_pair(ctx, {self.reg_num}, {self.reg_tcg()}= ); > + gen_write_reg_pair(ctx, {self.reg_num}, {self.reg_tcg()}); > """)) > def analyze_read(self, f, regno): > f.write(code_fmt(f"""\ > -- > 2.43.0 > > --000000000000e82ca2064514a717 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Fri, Nov 14,= 2025 at 5:00=E2=80=AFPM Taylor Simpson <ltaylorsimpson@gmail.com> wrote:
The gen_log_reg_write function is a me= mnant of the original Hexagon
target design.=C2=A0 With the addition of gen_analyze_funcs.py and the
ability to short-circuit a packet commit, this function can be
removed.

Note that the implementation of gen_log_reg_write contains a check
of the register mutability mask.=C2=A0 This is only needed for control
registers, so we move it to gen_write_ctrl_reg.

We do need the gen_log_reg_write_pair function, but the name is
now misleading, so we change the name go gen_write_reg_pair.

Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
---

Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>=
=C2=A0
=C2=A0target/hexagon/gen_tcg.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 7 +--
=C2=A0target/hexagon/genptr.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 1 -
=C2=A0target/hexagon/genptr.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 64 ++++++++-------------
=C2=A0target/hexagon/idef-parser/parser-helpers.c |=C2=A0 2 +-
=C2=A0target/hexagon/README=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 10 ++--
=C2=A0target/hexagon/gen_tcg_funcs.py=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0|=C2=A0 1 -
=C2=A0target/hexagon/hex_common.py=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 | 14 ++---
=C2=A07 files changed, 40 insertions(+), 59 deletions(-)

diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 8a3b801287..10123336b1 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -509,10 +509,9 @@
=C2=A0/* sub-instruction version (no RxV, so handle it manually) */
=C2=A0#define fGEN_TCG_SS2_allocframe(SHORTCODE) \
=C2=A0 =C2=A0 =C2=A0do { \
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 TCGv r29 =3D tcg_temp_new(); \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 TCGv r29 =3D get_result_gpr(ctx, HEX_REG_SP); = \
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_gen_mov_tl(r29, hex_gpr[HEX_REG_SP]);= \
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gen_allocframe(ctx, r29, uiV); \
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 gen_log_reg_write(ctx, HEX_REG_SP, r29); \
=C2=A0 =C2=A0 =C2=A0} while (0)

=C2=A0/*
@@ -528,7 +527,7 @@
=C2=A0 =C2=A0 =C2=A0do { \
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0TCGv_i64 r31_30 =3D tcg_temp_new_i64(); \=
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gen_deallocframe(ctx, r31_30, hex_gpr[HEX= _REG_FP]); \
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 gen_log_reg_write_pair(ctx, HEX_REG_FP, r31_30= ); \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 gen_write_reg_pair(ctx, HEX_REG_FP, r31_30); \=
=C2=A0 =C2=A0 =C2=A0} while (0)

=C2=A0/*
@@ -546,7 +545,7 @@
=C2=A0 =C2=A0 =C2=A0do { \
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0TCGv_i64 RddV =3D get_result_gpr_pair(ctx= , HEX_REG_FP); \
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gen_return(ctx, RddV, hex_gpr[HEX_REG_FP]= ); \
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 gen_log_reg_write_pair(ctx, HEX_REG_FP, RddV);= \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 gen_write_reg_pair(ctx, HEX_REG_FP, RddV); \ =C2=A0 =C2=A0 =C2=A0} while (0)

=C2=A0/*
diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h
index a4b43c2910..d932255042 100644
--- a/target/hexagon/genptr.h
+++ b/target/hexagon/genptr.h
@@ -37,7 +37,6 @@ TCGv gen_read_reg(TCGv result, int num);
=C2=A0TCGv gen_read_preg(TCGv pred, uint8_t num);
=C2=A0TCGv get_result_gpr(DisasContext *ctx, int rnum);
=C2=A0TCGv get_result_pred(DisasContext *ctx, int pnum);
-void gen_log_reg_write(DisasContext *ctx, int rnum, TCGv val);
=C2=A0void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val);
=C2=A0void gen_set_usr_field(DisasContext *ctx, int field, TCGv val);
=C2=A0void gen_set_usr_fieldi(DisasContext *ctx, int field, int x);
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index cecaece4ae..e58021ed6c 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -94,25 +94,17 @@ static TCGv_i64 get_result_gpr_pair(DisasContext *ctx, = int rnum)
=C2=A0 =C2=A0 =C2=A0return result;
=C2=A0}

-void gen_log_reg_write(DisasContext *ctx, int rnum, TCGv val)
-{
-=C2=A0 =C2=A0 const target_ulong reg_mask =3D reg_immut_masks[rnum];
-
-=C2=A0 =C2=A0 gen_masked_reg_write(val, hex_gpr[rnum], reg_mask);
-=C2=A0 =C2=A0 tcg_gen_mov_tl(get_result_gpr(ctx, rnum), val);
-}
-
-static void gen_log_reg_write_pair(DisasContext *ctx, int rnum, TCGv_i64 v= al)
+static void gen_write_reg_pair(DisasContext *ctx, int rnum, TCGv_i64 val)<= br> =C2=A0{
=C2=A0 =C2=A0 =C2=A0TCGv val32 =3D tcg_temp_new();

=C2=A0 =C2=A0 =C2=A0/* Low word */
=C2=A0 =C2=A0 =C2=A0tcg_gen_extrl_i64_i32(val32, val);
-=C2=A0 =C2=A0 gen_log_reg_write(ctx, rnum, val32);
+=C2=A0 =C2=A0 tcg_gen_mov_tl(get_result_gpr(ctx, rnum), val32);

=C2=A0 =C2=A0 =C2=A0/* High word */
=C2=A0 =C2=A0 =C2=A0tcg_gen_extrh_i64_i32(val32, val);
-=C2=A0 =C2=A0 gen_log_reg_write(ctx, rnum + 1, val32);
+=C2=A0 =C2=A0 tcg_gen_mov_tl(get_result_gpr(ctx, rnum + 1), val32);
=C2=A0}

=C2=A0TCGv get_result_pred(DisasContext *ctx, int pnum)
@@ -240,7 +232,9 @@ static inline void gen_write_ctrl_reg(DisasContext *ctx= , int reg_num,
=C2=A0 =C2=A0 =C2=A0if (reg_num =3D=3D HEX_REG_P3_0_ALIASED) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gen_write_p3_0(ctx, val);
=C2=A0 =C2=A0 =C2=A0} else {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 gen_log_reg_write(ctx, reg_num, val);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 const target_ulong reg_mask =3D reg_immut_mask= s[reg_num];
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 gen_masked_reg_write(val, hex_gpr[reg_num], re= g_mask);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_mov_tl(get_result_gpr(ctx, reg_num), v= al);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (reg_num =3D=3D HEX_REG_QEMU_PKT_CNT) = {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ctx->num_packets =3D 0;<= br> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
@@ -256,23 +250,15 @@ static inline void gen_write_ctrl_reg(DisasContext *c= tx, int reg_num,
=C2=A0static inline void gen_write_ctrl_reg_pair(DisasContext *ctx, int reg= _num,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 TCGv_i64 val)
=C2=A0{
-=C2=A0 =C2=A0 if (reg_num =3D=3D HEX_REG_P3_0_ALIASED) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 TCGv result =3D get_result_gpr(ctx, reg_num + = 1);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 TCGv val32 =3D tcg_temp_new();
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_extrl_i64_i32(val32, val);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 gen_write_p3_0(ctx, val32);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_extrh_i64_i32(val32, val);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_mov_tl(result, val32);
-=C2=A0 =C2=A0 } else {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 gen_log_reg_write_pair(ctx, reg_num, val);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (reg_num =3D=3D HEX_REG_QEMU_PKT_CNT) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ctx->num_packets =3D 0;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ctx->num_insns =3D 0;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (reg_num =3D=3D HEX_REG_QEMU_HVX_CNT) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ctx->num_hvx_insns =3D 0;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
-=C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 TCGv val32 =3D tcg_temp_new();
+
+=C2=A0 =C2=A0 /* Low word */
+=C2=A0 =C2=A0 tcg_gen_extrl_i64_i32(val32, val);
+=C2=A0 =C2=A0 gen_write_ctrl_reg(ctx, reg_num, val32);
+
+=C2=A0 =C2=A0 /* High word */
+=C2=A0 =C2=A0 tcg_gen_extrh_i64_i32(val32, val);
+=C2=A0 =C2=A0 gen_write_ctrl_reg(ctx, reg_num + 1, val32);
=C2=A0}

=C2=A0TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign)
@@ -541,8 +527,8 @@ static inline void gen_loop0r(DisasContext *ctx, TCGv R= sV, int riV)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0fIMMEXT(riV);
=C2=A0 =C2=A0 =C2=A0fPCALIGN(riV);
-=C2=A0 =C2=A0 gen_log_reg_write(ctx, HEX_REG_LC0, RsV);
-=C2=A0 =C2=A0 gen_log_reg_write(ctx, HEX_REG_SA0, tcg_constant_tl(ctx->= pkt->pc + riV));
+=C2=A0 =C2=A0 tcg_gen_mov_tl(get_result_gpr(ctx, HEX_REG_LC0), RsV);
+=C2=A0 =C2=A0 tcg_gen_movi_tl(get_result_gpr(ctx, HEX_REG_SA0), ctx->pk= t->pc + riV);
=C2=A0 =C2=A0 =C2=A0gen_set_usr_fieldi(ctx, USR_LPCFG, 0);
=C2=A0}

@@ -555,8 +541,8 @@ static inline void gen_loop1r(DisasContext *ctx, TCGv R= sV, int riV)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0fIMMEXT(riV);
=C2=A0 =C2=A0 =C2=A0fPCALIGN(riV);
-=C2=A0 =C2=A0 gen_log_reg_write(ctx, HEX_REG_LC1, RsV);
-=C2=A0 =C2=A0 gen_log_reg_write(ctx, HEX_REG_SA1, tcg_constant_tl(ctx->= pkt->pc + riV));
+=C2=A0 =C2=A0 tcg_gen_mov_tl(get_result_gpr(ctx, HEX_REG_LC1), RsV);
+=C2=A0 =C2=A0 tcg_gen_movi_tl(get_result_gpr(ctx, HEX_REG_SA1), ctx->pk= t->pc + riV);
=C2=A0}

=C2=A0static void gen_loop1i(DisasContext *ctx, int count, int riV)
@@ -568,8 +554,8 @@ static void gen_ploopNsr(DisasContext *ctx, int N, TCGv= RsV, int riV)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0fIMMEXT(riV);
=C2=A0 =C2=A0 =C2=A0fPCALIGN(riV);
-=C2=A0 =C2=A0 gen_log_reg_write(ctx, HEX_REG_LC0, RsV);
-=C2=A0 =C2=A0 gen_log_reg_write(ctx, HEX_REG_SA0, tcg_constant_tl(ctx->= pkt->pc + riV));
+=C2=A0 =C2=A0 tcg_gen_mov_tl(get_result_gpr(ctx, HEX_REG_LC0), RsV);
+=C2=A0 =C2=A0 tcg_gen_movi_tl(get_result_gpr(ctx, HEX_REG_SA0), ctx->pk= t->pc + riV);
=C2=A0 =C2=A0 =C2=A0gen_set_usr_fieldi(ctx, USR_LPCFG, N);
=C2=A0 =C2=A0 =C2=A0gen_log_pred_write(ctx, 3, tcg_constant_tl(0));
=C2=A0}
@@ -773,25 +759,23 @@ static void gen_framecheck(TCGv EA, int framesize)
=C2=A0static void gen_allocframe(DisasContext *ctx, TCGv r29, int framesize= )
=C2=A0{
-=C2=A0 =C2=A0 TCGv r30 =3D tcg_temp_new();
+=C2=A0 =C2=A0 TCGv r30 =3D get_result_gpr(ctx, HEX_REG_FP);
=C2=A0 =C2=A0 =C2=A0TCGv_i64 frame;
=C2=A0 =C2=A0 =C2=A0tcg_gen_addi_tl(r30, r29, -8);
=C2=A0 =C2=A0 =C2=A0frame =3D gen_frame_scramble();
=C2=A0 =C2=A0 =C2=A0gen_store8(tcg_env, r30, frame, ctx->insn->slot);=
-=C2=A0 =C2=A0 gen_log_reg_write(ctx, HEX_REG_FP, r30);
=C2=A0 =C2=A0 =C2=A0gen_framecheck(r30, framesize);
=C2=A0 =C2=A0 =C2=A0tcg_gen_subi_tl(r29, r30, framesize);
=C2=A0}

=C2=A0static void gen_deallocframe(DisasContext *ctx, TCGv_i64 r31_30, TCGv= r30)
=C2=A0{
-=C2=A0 =C2=A0 TCGv r29 =3D tcg_temp_new();
+=C2=A0 =C2=A0 TCGv r29 =3D get_result_gpr(ctx, HEX_REG_SP);
=C2=A0 =C2=A0 =C2=A0TCGv_i64 frame =3D tcg_temp_new_i64();
=C2=A0 =C2=A0 =C2=A0gen_load_frame(ctx, frame, r30);
=C2=A0 =C2=A0 =C2=A0gen_frame_unscramble(frame);
=C2=A0 =C2=A0 =C2=A0tcg_gen_mov_i64(r31_30, frame);
=C2=A0 =C2=A0 =C2=A0tcg_gen_addi_tl(r29, r30, 8);
-=C2=A0 =C2=A0 gen_log_reg_write(ctx, HEX_REG_SP, r29);
=C2=A0}
=C2=A0#endif

@@ -833,7 +817,7 @@ static void gen_cond_return_subinsn(DisasContext *ctx, = TCGCond cond, TCGv pred)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0TCGv_i64 RddV =3D get_result_gpr_pair(ctx, HEX_REG_FP);=
=C2=A0 =C2=A0 =C2=A0gen_cond_return(ctx, RddV, hex_gpr[HEX_REG_FP], pred, c= ond);
-=C2=A0 =C2=A0 gen_log_reg_write_pair(ctx, HEX_REG_FP, RddV);
+=C2=A0 =C2=A0 gen_write_reg_pair(ctx, HEX_REG_FP, RddV);
=C2=A0}

=C2=A0static void gen_endloop0(DisasContext *ctx)
diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/i= def-parser/parser-helpers.c
index 1dc52b4e02..f5802ceadb 100644
--- a/target/hexagon/idef-parser/parser-helpers.c
+++ b/target/hexagon/idef-parser/parser-helpers.c
@@ -1315,7 +1315,7 @@ void gen_write_reg(Context *c, YYLTYPE *locp, HexValu= e *reg, HexValue *value)
=C2=A0 =C2=A0 =C2=A0value_m =3D rvalue_materialize(c, locp, &value_m);<= br> =C2=A0 =C2=A0 =C2=A0OUT(c,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0locp,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 "gen_log_reg_write(ctx, ", &reg-= >reg.id, ", ",
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 "tcg_gen_mov_tl(get_result_gpr(ctx, "= ;, &reg->reg.id, "), ",
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&value_m, ");\n");
=C2=A0}

diff --git a/target/hexagon/README b/target/hexagon/README
index ca617e3364..1938c91af8 100644
--- a/target/hexagon/README
+++ b/target/hexagon/README
@@ -80,12 +80,14 @@ tcg_funcs_generated.c.inc
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0Insn *insn,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0Packet *pkt)
=C2=A0 =C2=A0 =C2=A0{
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 TCGv RdV =3D tcg_temp_new();
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 Insn *insn G_GNUC_UNUSED =3D ctx->insn;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0const int RdN =3D insn->regno[0];
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 TCGv RsV =3D hex_gpr[insn->regno[1]];
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 TCGv RtV =3D hex_gpr[insn->regno[2]];
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 TCGv RdV =3D get_result_gpr(ctx, RdN);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 const int RsN =3D insn->regno[1];
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 TCGv RsV =3D hex_gpr[RsN];
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 const int RtN =3D insn->regno[2];
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 TCGv RtV =3D hex_gpr[RtN];
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gen_helper_A2_add(RdV, tcg_env, RsV, RtV)= ;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 gen_log_reg_write(ctx, RdN, RdV);
=C2=A0 =C2=A0 =C2=A0}

=C2=A0helper_funcs_generated.c.inc
diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs= .py
index c2ba91ddc0..bd241afde1 100755
--- a/target/hexagon/gen_tcg_funcs.py
+++ b/target/hexagon/gen_tcg_funcs.py
@@ -35,7 +35,6 @@
=C2=A0##=C2=A0 =C2=A0 =C2=A0 =C2=A0 TCGv RsV =3D hex_gpr[insn->regno[1]]= ;
=C2=A0##=C2=A0 =C2=A0 =C2=A0 =C2=A0 TCGv RtV =3D hex_gpr[insn->regno[2]]= ;
=C2=A0##=C2=A0 =C2=A0 =C2=A0 =C2=A0 <GEN>
-##=C2=A0 =C2=A0 =C2=A0 =C2=A0 gen_log_reg_write(ctx, RdN, RdV);
=C2=A0##=C2=A0 =C2=A0 }
=C2=A0##
=C2=A0##=C2=A0 =C2=A0 =C2=A0 =C2=A0where <GEN> depends on hex_common.= skip_qemu_helper(tag)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index 6803908718..093def9386 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -452,9 +452,8 @@ def decl_tcg(self, f, tag, regno):
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0TCGv {self.reg_tcg()} =3D g= et_result_gpr(ctx, {self.reg_num});
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"""))
=C2=A0 =C2=A0 =C2=A0def log_write(self, f, tag):
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 f.write(code_fmt(f"""\
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 gen_log_reg_write(ctx, {self.reg= _num}, {self.reg_tcg()});
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 """))
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 ## No write needed
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return
=C2=A0 =C2=A0 =C2=A0def analyze_write(self, f, tag, regno):
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0predicated =3D "true" if is_pre= dicated(tag) else "false"
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0f.write(code_fmt(f"""\
@@ -496,9 +495,8 @@ def decl_tcg(self, f, tag, regno):
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_gen_mov_t= l({self.reg_tcg()}, hex_gpr[{self.reg_num}]);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"""))
=C2=A0 =C2=A0 =C2=A0def log_write(self, f, tag):
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 f.write(code_fmt(f"""\
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 gen_log_reg_write(ctx, {self.reg= _num}, {self.reg_tcg()});
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 """))
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 ## No write needed
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return
=C2=A0 =C2=A0 =C2=A0def analyze_read(self, f, regno):
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0f.write(code_fmt(f"""\
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ctx_log_reg_read(ctx, {self= .reg_num});
@@ -630,7 +628,7 @@ def decl_tcg(self, f, tag, regno):
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"""))
=C2=A0 =C2=A0 =C2=A0def log_write(self, f, tag):
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0f.write(code_fmt(f"""\
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 gen_log_reg_write_pair(ctx, {sel= f.reg_num}, {self.reg_tcg()});
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 gen_write_reg_pair(ctx, {self.re= g_num}, {self.reg_tcg()});
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"""))
=C2=A0 =C2=A0 =C2=A0def analyze_write(self, f, tag, regno):
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0predicated =3D "true" if is_pre= dicated(tag) else "false"
@@ -664,7 +662,7 @@ def decl_tcg(self, f, tag, regno):
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"""))
=C2=A0 =C2=A0 =C2=A0def log_write(self, f, tag):
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0f.write(code_fmt(f"""\
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 gen_log_reg_write_pair(ctx, {sel= f.reg_num}, {self.reg_tcg()});
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 gen_write_reg_pair(ctx, {self.re= g_num}, {self.reg_tcg()});
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"""))
=C2=A0 =C2=A0 =C2=A0def analyze_read(self, f, regno):
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0f.write(code_fmt(f"""\
--
2.43.0

--000000000000e82ca2064514a717--