From: Julio Guerra <guerr@julio.in>
To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Cc: Julio Guerra <guerr@julio.in>, Alexander Graf <agraf@suse.de>
Subject: Re: [Qemu-devel] [PATCH v2] e600 core for MPC86xx processors
Date: Thu, 6 Jun 2013 08:20:05 +0200 [thread overview]
Message-ID: <CAFAwnGMfc-+SUfoA-nnaytG0fK3wV91uMAsksk4R5tqQp=mqFA@mail.gmail.com> (raw)
In-Reply-To: <1369590093-9086-1-git-send-email-guerr@julio.in>
ping
2013/5/26 Julio Guerra <guerr@julio.in>:
> MPC86xx processors are based on the e600 core, which is not the case
> in qemu where it is based on the 7400 processor.
>
> This patch creates the e600 core and instantiates the MPC86xx
> processors based on it. Therefore, adding the high BATs and the SPRG
> 4..7 registers, which are e600-specific [1].
>
> This allows to define the MPC8610 processor too and my program running
> on a real MPC8610 target is now able to run on qemu :)
>
> [1] http://cache.freescale.com/files/32bit/doc/ref_manual/E600CORERM.pdf
>
> Signed-off-by: Julio Guerra <guerr@julio.in>
> ---
> target-ppc/cpu-models.c | 10 ++--
> target-ppc/cpu-models.h | 4 +-
> target-ppc/translate_init.c | 122 ++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 127 insertions(+), 9 deletions(-)
>
> diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
> index 17f56b7..8a2ab50 100644
> --- a/target-ppc/cpu-models.c
> +++ b/target-ppc/cpu-models.c
> @@ -792,17 +792,15 @@
> POWERPC_DEF_SVR("MPC8572E", "MPC8572E",
> CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2)
> /* e600 family */
> - POWERPC_DEF("e600", CPU_POWERPC_e600, 7400,
> + POWERPC_DEF("e600", CPU_POWERPC_e600, e600,
> "PowerPC e600 core")
> /* PowerPC e600 microcontrollers */
> -#if defined(TODO)
> POWERPC_DEF_SVR("MPC8610", "MPC8610",
> - CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400)
> -#endif
> + CPU_POWERPC_MPC8610, POWERPC_SVR_8610, e600)
> POWERPC_DEF_SVR("MPC8641", "MPC8641",
> - CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400)
> + CPU_POWERPC_MPC8641, POWERPC_SVR_8641, e600)
> POWERPC_DEF_SVR("MPC8641D", "MPC8641D",
> - CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400)
> + CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, e600)
> /* 32 bits "classic" PowerPC */
> /* PowerPC 6xx family */
> POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601,
> diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h
> index a94f835..8ba96bb 100644
> --- a/target-ppc/cpu-models.h
> +++ b/target-ppc/cpu-models.h
> @@ -731,9 +731,7 @@ enum {
> POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
> POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
> POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
> -#if 0
> - POWERPC_SVR_8610 = xxx,
> -#endif
> + POWERPC_SVR_8610 = 0x80A00011,
> POWERPC_SVR_8641 = 0x80900021,
> POWERPC_SVR_8641D = 0x80900121,
> };
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 021a31e..916fe0d 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -6525,2 +6525,2 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
> POWERPC_FLAG_BUS_CLK;
> }
>
> +static void init_proc_e600(CPUPPCState *env)
> +{
> + gen_spr_ne_601(env);
> + gen_spr_7xx(env);
> + /* Time base */
> + gen_tbl(env);
> + /* 74xx specific SPR */
> + gen_spr_74xx(env);
> + /* XXX : not implemented */
> + spr_register(env, SPR_UBAMR, "UBAMR",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> + /* XXX : not implemented */
> + spr_register(env, SPR_LDSTCR, "LDSTCR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + /* XXX : not implemented */
> + spr_register(env, SPR_ICTRL, "ICTRL",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + /* XXX : not implemented */
> + spr_register(env, SPR_MSSSR0, "MSSSR0",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + /* XXX : not implemented */
> + spr_register(env, SPR_PMC5, "PMC5",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + /* XXX : not implemented */
> + spr_register(env, SPR_UPMC5, "UPMC5",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> + /* XXX : not implemented */
> + spr_register(env, SPR_PMC6, "PMC6",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + /* XXX : not implemented */
> + spr_register(env, SPR_UPMC6, "UPMC6",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> + /* SPRGs */
> + spr_register(env, SPR_SPRG4, "SPRG4",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + spr_register(env, SPR_USPRG4, "USPRG4",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> + spr_register(env, SPR_SPRG5, "SPRG5",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + spr_register(env, SPR_USPRG5, "USPRG5",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> + spr_register(env, SPR_SPRG6, "SPRG6",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + spr_register(env, SPR_USPRG6, "USPRG6",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> + spr_register(env, SPR_SPRG7, "SPRG7",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + spr_register(env, SPR_USPRG7, "USPRG7",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> + /* Memory management */
> + gen_low_BATs(env);
> + gen_high_BATs(env);
> + gen_74xx_soft_tlb(env, 128, 2);
> + init_excp_7450(env);
> + env->dcache_line_size = 32;
> + env->icache_line_size = 32;
> + /* Allocate hardware IRQ controller */
> + ppc6xx_irq_init(env);
> +}
> +
> +POWERPC_FAMILY(e600)(ObjectClass* oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> +
> + dc->desc = "PowerPC e600";
> + pcc->init_proc = init_proc_e600;
> + pcc->check_pow = check_pow_hid0_74xx;
> + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
> + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
> + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> + PPC_FLOAT_STFIWX |
> + PPC_CACHE | PPC_CACHE_ICBI |
> + PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
> + PPC_MEM_SYNC | PPC_MEM_EIEIO |
> + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
> + PPC_MEM_TLBIA | PPC_74xx_TLB |
> + PPC_SEGMENT | PPC_EXTERN |
> + PPC_ALTIVEC;
> + pcc->insns_flags2 = PPC_NONE;
> + pcc->msr_mask = 0x000000000205FF77ULL;
> + pcc->mmu_model = POWERPC_MMU_32B;
> + pcc->excp_model = POWERPC_EXCP_74xx;
> + pcc->bus_model = PPC_FLAGS_INPUT_6xx;
> + pcc->bfd_mach = bfd_mach_ppc_7400;
> + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
> + POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
> + POWERPC_FLAG_BUS_CLK;
> +}
> +
> #if defined (TARGET_PPC64)
> #if defined(CONFIG_USER_ONLY)
> #define POWERPC970_HID5_INIT 0x00000080
> --
> 1.8.1.4
--
Julio Guerra
next prev parent reply other threads:[~2013-06-06 6:20 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-05-26 17:41 [Qemu-devel] [PATCH v2] e600 core for MPC86xx processors Julio Guerra
2013-06-06 6:20 ` Julio Guerra [this message]
2013-06-06 11:44 ` Andreas Färber
2013-06-06 16:31 ` Scott Wood
2013-06-07 13:44 ` Julio Guerra
2013-06-13 6:32 ` Julio Guerra
2013-06-20 23:16 ` Alexander Graf
2013-06-21 12:01 ` Julio Guerra
2013-06-21 12:03 ` Alexander Graf
2013-06-24 4:14 ` Alexey Kardashevskiy
2013-06-24 6:13 ` Julio Guerra
2013-06-24 6:41 ` Alexander Graf
2013-06-22 0:50 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
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