From: Peter Maydell <peter.maydell@linaro.org>
To: Leon Alrae <leon.alrae@imgtec.com>
Cc: QEMU Developers <qemu-devel@nongnu.org>,
Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [Qemu-devel] [PULL 00/21] target-mips queue for 2.6
Date: Tue, 29 Mar 2016 20:52:55 +0100 [thread overview]
Message-ID: <CAFEAcA-+iLRw+EtSHr1aW784EbKO2o95erWFKcTuaPHy71zJGw@mail.gmail.com> (raw)
In-Reply-To: <1459245425-4374-1-git-send-email-leon.alrae@imgtec.com>
On 29 March 2016 at 10:56, Leon Alrae <leon.alrae@imgtec.com> wrote:
> Hi,
>
> Here's MIPS pull request which adds initial implementation of MIPS Coherent
> Processing System including Cluster Power Controller and Global Config
> Registers allowing the guest to control the start of other Virtual
> Processors after reset. Also, this pullreq adds Inter-Thread Communication
> Unit and MAAR.
>
> Thanks,
> Leon
>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Cc: Aurelien Jarno <aurelien@aurel32.net>
>
> The following changes since commit b68a80139e37e806f004237e55311ebc42151434:
>
> Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20160324' into staging (2016-03-24 16:24:02 +0000)
>
> are available in the git repository at:
>
> git://github.com/lalrae/qemu.git tags/mips-20160329
>
> for you to fetch changes up to e9f517b73dab520de05b871359d2beedf8b04e53:
>
> target-mips: add MAAR, MAARI register (2016-03-28 19:27:09 +0100)
>
> ----------------------------------------------------------------
> MIPS patches 2016-03-29
>
> Changes:
> * add initial MIPS CPS support
> * implement ITU block
> * implement MAAR
Hi. I'm afraid this doesn't compile:
/home/petmay01/linaro/qemu-for-merges/hw/misc/mips_cmgcr.c: In
function ‘mips_gcr_init’:
/home/petmay01/linaro/qemu-for-merges/hw/misc/mips_cmgcr.c:107:31:
error: ‘error_abort’ undeclared (first use in this function)
&error_abort);
^
/home/petmay01/linaro/qemu-for-merges/hw/misc/mips_cmgcr.c:107:31:
note: each undeclared identifier is reported only once for each
function it appears in
CC mips64-softmmu/hw/misc/mips_itu.o
make[1]: *** [hw/misc/mips_cmgcr.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC mips64el-softmmu/hw/misc/mips_cmgcr.o
/home/petmay01/linaro/qemu-for-merges/hw/misc/mips_cpc.c: In function
‘mips_cpc_realize’:
/home/petmay01/linaro/qemu-for-merges/hw/misc/mips_cpc.c:119:9: error:
implicit declaration of function ‘error_setg’
[-Werror=implicit-function-declaration]
error_setg(errp,
^
/home/petmay01/linaro/qemu-for-merges/hw/misc/mips_cpc.c:119:9: error:
nested extern declaration of ‘error_setg’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
(and similar other errors).
I think you've unfortunately collided with a patch in Paolo's
recent pull request which changes how we handle qapi/error.h
(it's no longer pulled in by osdep.h by default); see commit
da34e65cb.
thanks
-- PMM
prev parent reply other threads:[~2016-03-29 19:53 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-29 9:56 [Qemu-devel] [PULL 00/21] target-mips queue for 2.6 Leon Alrae
2016-03-29 9:56 ` [Qemu-devel] [PULL 01/21] hw/mips: implement generic MIPS Coherent Processing System container Leon Alrae
2016-03-29 9:56 ` [Qemu-devel] [PULL 02/21] target-mips: add CMGCRBase register Leon Alrae
2016-03-29 9:56 ` [Qemu-devel] [PULL 03/21] hw/mips: add initial Global Config Register support Leon Alrae
2016-03-29 9:56 ` [Qemu-devel] [PULL 04/21] hw/mips/cps: create GCR block inside CPS Leon Alrae
2016-03-29 9:56 ` [Qemu-devel] [PULL 05/21] hw/mips: add initial Cluster Power Controller support Leon Alrae
2016-03-29 9:56 ` [Qemu-devel] [PULL 06/21] hw/mips/cps: create CPC block inside CPS Leon Alrae
2016-03-29 9:56 ` [Qemu-devel] [PULL 07/21] hw/mips_malta: remove CPUMIPSState from the write_bootloader() Leon Alrae
2016-03-29 9:56 ` [Qemu-devel] [PULL 08/21] hw/mips_malta: remove redundant irq and clock init Leon Alrae
2016-03-29 9:56 ` [Qemu-devel] [PULL 09/21] hw/mips_malta: move CPU creation to a separate function Leon Alrae
2016-03-29 9:56 ` [Qemu-devel] [PULL 10/21] hw/mips_malta: add CPS to Malta board Leon Alrae
2016-03-29 9:56 ` [Qemu-devel] [PULL 11/21] target-mips: enable CM GCR in MIPS64R6-generic CPU Leon Alrae
2016-03-29 9:56 ` [Qemu-devel] [PULL 12/21] hw/mips: implement ITC Configuration Tags and Storage Cells Leon Alrae
2016-03-29 9:56 ` [Qemu-devel] [PULL 13/21] hw/mips: implement ITC Storage - Control View Leon Alrae
2016-03-29 9:56 ` [Qemu-devel] [PULL 14/21] hw/mips: implement ITC Storage - Empty/Full Sync and Try Views Leon Alrae
2016-03-29 9:56 ` [Qemu-devel] [PULL 15/21] hw/mips: implement ITC Storage - P/V " Leon Alrae
2016-03-29 9:57 ` [Qemu-devel] [PULL 16/21] hw/mips: implement ITC Storage - Bypass View Leon Alrae
2016-03-29 9:57 ` [Qemu-devel] [PULL 17/21] target-mips: check CP0 enabled for CACHE instruction also in R6 Leon Alrae
2016-03-29 9:57 ` [Qemu-devel] [PULL 18/21] target-mips: make ITC Configuration Tags accessible to the CPU Leon Alrae
2016-03-29 9:57 ` [Qemu-devel] [PULL 19/21] hw/mips/cps: enable ITU for multithreading processors Leon Alrae
2016-03-29 9:57 ` [Qemu-devel] [PULL 20/21] target-mips: use CP0_CHECK for gen_m{f|t}hc0 Leon Alrae
2016-03-29 9:57 ` [Qemu-devel] [PULL 21/21] target-mips: add MAAR, MAARI register Leon Alrae
2016-03-29 19:52 ` Peter Maydell [this message]
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