[PATCH v3 0/3] hw/i2c: smbus: Reset fixes

[PATCH v3 0/3] hw/i2c: smbus: Reset fixes

[Joe Komlodi]

Changelog:

v2 -> v3
Patch 1
- Removed I3CBus class definition, since it was unneeded.
- whitespace fixes
- Changed enter_reset to hold_reset

Patch 2
- Moved pointer returned by object_get_canonical_path outside of printf
  so it can be freed

Patch 3
- Changed enter_reset to hold_reset

v1 -> v2
- Dropped 4th patch "hw/i2c: smbus: mux: Reset SMBusDevice state
on reset". After more testing and Corey's comment, I realized it
wasn't needed.

Original message:

Hi all,

This series adds some resets for SMBus and for the I2C core. Along with
it, we make SMBus slave error printing a little more helpful.

These reset issues were very infrequent, they would maybe occur in 1 out
of hundreds of resets in our testing, but the way they happen is pretty
straightforward.

Basically as long as a reset happens in the middle of a transaction, the
state of the old transaction would still partially be there after the
reset. Once a new transaction comes in, the partial stale state can
cause the new transaction to incorrectly fail.

Thanks,
Joe

Joe Komlodi (3):
  hw/i2c: core: Add reset
  hw/i2c/smbus_slave: Add object path on error prints
  hw/i2c: smbus_slave: Reset state on reset

 hw/i2c/core.c        | 19 +++++++++++++++++++
 hw/i2c/smbus_slave.c | 17 +++++++++++++++--
 include/hw/i2c/i2c.h |  2 +-
 3 files changed, 35 insertions(+), 3 deletions(-)

-- 
2.43.0.594.gd9cf4e227d-goog

[PATCH v3 1/3] hw/i2c: core: Add reset

[Joe Komlodi]

It's possible for a reset to come in the middle of a transaction, which
causes the bus to be in an old state when a new transaction comes in.

Signed-off-by: Joe Komlodi <komlodi@google.com>
---
 hw/i2c/core.c        | 19 +++++++++++++++++++
 include/hw/i2c/i2c.h |  2 +-
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/hw/i2c/core.c b/hw/i2c/core.c
index 4cf30b2c86..3128067bba 100644
--- a/hw/i2c/core.c
+++ b/hw/i2c/core.c
@@ -23,10 +23,29 @@ static Property i2c_props[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
+static void i2c_bus_hold_reset(Object *obj)
+{
+    I2CBus *bus = I2C_BUS(obj);
+    I2CNode *node, *next;
+
+    bus->broadcast = false;
+    QLIST_FOREACH_SAFE(node, &bus->current_devs, next, next) {
+        QLIST_REMOVE(node, next);
+        g_free(node);
+    }
+}
+
+static void i2c_bus_class_init(ObjectClass *klass, void *data)
+{
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    rc->phases.hold = i2c_bus_hold_reset;
+}
+
 static const TypeInfo i2c_bus_info = {
     .name = TYPE_I2C_BUS,
     .parent = TYPE_BUS,
     .instance_size = sizeof(I2CBus),
+    .class_init = i2c_bus_class_init,
 };
 
 static int i2c_bus_pre_save(void *opaque)
diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
index 2a3abacd1b..49580e30e2 100644
--- a/include/hw/i2c/i2c.h
+++ b/include/hw/i2c/i2c.h
@@ -64,7 +64,7 @@ struct I2CSlave {
 };
 
 #define TYPE_I2C_BUS "i2c-bus"
-OBJECT_DECLARE_SIMPLE_TYPE(I2CBus, I2C_BUS)
+OBJECT_DECLARE_TYPE(I2CBus, I2CBusClass, I2C_BUS)
 
 typedef struct I2CNode I2CNode;
 
-- 
2.43.0.594.gd9cf4e227d-goog

Re: [PATCH v3 1/3] hw/i2c: core: Add reset

[Peter Maydell]

On Fri, 2 Feb 2024 at 20:48, Joe Komlodi <komlodi@google.com> wrote:
>
> It's possible for a reset to come in the middle of a transaction, which
> causes the bus to be in an old state when a new transaction comes in.
>
> Signed-off-by: Joe Komlodi <komlodi@google.com>
> ---
>  hw/i2c/core.c        | 19 +++++++++++++++++++
>  include/hw/i2c/i2c.h |  2 +-
>  2 files changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/hw/i2c/core.c b/hw/i2c/core.c
> index 4cf30b2c86..3128067bba 100644
> --- a/hw/i2c/core.c
> +++ b/hw/i2c/core.c
> @@ -23,10 +23,29 @@ static Property i2c_props[] = {
>      DEFINE_PROP_END_OF_LIST(),
>  };
>
> +static void i2c_bus_hold_reset(Object *obj)
> +{
> +    I2CBus *bus = I2C_BUS(obj);
> +    I2CNode *node, *next;
> +
> +    bus->broadcast = false;
> +    QLIST_FOREACH_SAFE(node, &bus->current_devs, next, next) {
> +        QLIST_REMOVE(node, next);
> +        g_free(node);
> +    }
> +}

This does what it says it's going to do; but I think it
would be good to hear from Corey whether it's better to
do this, or instead to call i2c_end_transfer() in the
reset-enter phase.

Mostly QEMU's "reset" is like power-cycling, in which case
I guess that what we have here where we just forget about
the in-progress transfer and assume the device on the other
end is also going to reset back to a neutral state is what
we want.

Does i2c have a concept of a bus-level "reset" operation?

> +
> +static void i2c_bus_class_init(ObjectClass *klass, void *data)
> +{
> +    ResettableClass *rc = RESETTABLE_CLASS(klass);
> +    rc->phases.hold = i2c_bus_hold_reset;
> +}
> +
>  static const TypeInfo i2c_bus_info = {
>      .name = TYPE_I2C_BUS,
>      .parent = TYPE_BUS,
>      .instance_size = sizeof(I2CBus),
> +    .class_init = i2c_bus_class_init,
>  };



>  static int i2c_bus_pre_save(void *opaque)
> diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
> index 2a3abacd1b..49580e30e2 100644
> --- a/include/hw/i2c/i2c.h
> +++ b/include/hw/i2c/i2c.h
> @@ -64,7 +64,7 @@ struct I2CSlave {
>  };
>
>  #define TYPE_I2C_BUS "i2c-bus"
> -OBJECT_DECLARE_SIMPLE_TYPE(I2CBus, I2C_BUS)
> +OBJECT_DECLARE_TYPE(I2CBus, I2CBusClass, I2C_BUS)

I don't think you need this change any more ?

thanks
-- PMM

Re: [PATCH v3 1/3] hw/i2c: core: Add reset

[Joe Komlodi]

On Thu, Feb 8, 2024 at 8:39 AM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Fri, 2 Feb 2024 at 20:48, Joe Komlodi <komlodi@google.com> wrote:
> >
> > It's possible for a reset to come in the middle of a transaction, which
> > causes the bus to be in an old state when a new transaction comes in.
> >
> > Signed-off-by: Joe Komlodi <komlodi@google.com>
> > ---
> >  hw/i2c/core.c        | 19 +++++++++++++++++++
> >  include/hw/i2c/i2c.h |  2 +-
> >  2 files changed, 20 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/i2c/core.c b/hw/i2c/core.c
> > index 4cf30b2c86..3128067bba 100644
> > --- a/hw/i2c/core.c
> > +++ b/hw/i2c/core.c
> > @@ -23,10 +23,29 @@ static Property i2c_props[] = {
> >      DEFINE_PROP_END_OF_LIST(),
> >  };
> >
> > +static void i2c_bus_hold_reset(Object *obj)
> > +{
> > +    I2CBus *bus = I2C_BUS(obj);
> > +    I2CNode *node, *next;
> > +
> > +    bus->broadcast = false;
> > +    QLIST_FOREACH_SAFE(node, &bus->current_devs, next, next) {
> > +        QLIST_REMOVE(node, next);
> > +        g_free(node);
> > +    }
> > +}
>
> This does what it says it's going to do; but I think it
> would be good to hear from Corey whether it's better to
> do this, or instead to call i2c_end_transfer() in the
> reset-enter phase.

i2c_end_transfer() might actually make more sense (explained a little
more below). I'll see what Corey says though.
>
> Mostly QEMU's "reset" is like power-cycling, in which case
> I guess that what we have here where we just forget about
> the in-progress transfer and assume the device on the other
> end is also going to reset back to a neutral state is what
> we want.
>
> Does i2c have a concept of a bus-level "reset" operation?
>
Not really, as far as I know.
On hardware I believe if a reset happened in the middle of a
transaction it would just look like a transaction ending from the
target's PoV.

> > +
> > +static void i2c_bus_class_init(ObjectClass *klass, void *data)
> > +{
> > +    ResettableClass *rc = RESETTABLE_CLASS(klass);
> > +    rc->phases.hold = i2c_bus_hold_reset;
> > +}
> > +
> >  static const TypeInfo i2c_bus_info = {
> >      .name = TYPE_I2C_BUS,
> >      .parent = TYPE_BUS,
> >      .instance_size = sizeof(I2CBus),
> > +    .class_init = i2c_bus_class_init,
> >  };
>
>
>
> >  static int i2c_bus_pre_save(void *opaque)
> > diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
> > index 2a3abacd1b..49580e30e2 100644
> > --- a/include/hw/i2c/i2c.h
> > +++ b/include/hw/i2c/i2c.h
> > @@ -64,7 +64,7 @@ struct I2CSlave {
> >  };
> >
> >  #define TYPE_I2C_BUS "i2c-bus"
> > -OBJECT_DECLARE_SIMPLE_TYPE(I2CBus, I2C_BUS)
> > +OBJECT_DECLARE_TYPE(I2CBus, I2CBusClass, I2C_BUS)
>
> I don't think you need this change any more ?

Oops, will fix in v4. I'll hold off on sending it until Corey gives
input on the reset behavior.

Thanks,
Joe
>
> thanks
> -- PMM

Re: [PATCH v3 1/3] hw/i2c: core: Add reset

[Corey Minyard]

On Thu, Feb 08, 2024 at 04:39:10PM +0000, Peter Maydell wrote:
> On Fri, 2 Feb 2024 at 20:48, Joe Komlodi <komlodi@google.com> wrote:
> >
> > It's possible for a reset to come in the middle of a transaction, which
> > causes the bus to be in an old state when a new transaction comes in.
> >
> > Signed-off-by: Joe Komlodi <komlodi@google.com>
> > ---
> >  hw/i2c/core.c        | 19 +++++++++++++++++++
> >  include/hw/i2c/i2c.h |  2 +-
> >  2 files changed, 20 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/i2c/core.c b/hw/i2c/core.c
> > index 4cf30b2c86..3128067bba 100644
> > --- a/hw/i2c/core.c
> > +++ b/hw/i2c/core.c
> > @@ -23,10 +23,29 @@ static Property i2c_props[] = {
> >      DEFINE_PROP_END_OF_LIST(),
> >  };
> >
> > +static void i2c_bus_hold_reset(Object *obj)
> > +{
> > +    I2CBus *bus = I2C_BUS(obj);
> > +    I2CNode *node, *next;
> > +
> > +    bus->broadcast = false;
> > +    QLIST_FOREACH_SAFE(node, &bus->current_devs, next, next) {
> > +        QLIST_REMOVE(node, next);
> > +        g_free(node);
> > +    }
> > +}
> 
> This does what it says it's going to do; but I think it
> would be good to hear from Corey whether it's better to
> do this, or instead to call i2c_end_transfer() in the
> reset-enter phase.

Sorry, I missed this, I'm having major chaos going on right now in my
life.

I don't think i2c_end_transfer() is the right thing to do.  The transfer
has not cleanly ended, it is just forgotten.

> 
> Mostly QEMU's "reset" is like power-cycling, in which case
> I guess that what we have here where we just forget about
> the in-progress transfer and assume the device on the other
> end is also going to reset back to a neutral state is what
> we want.
> 
> Does i2c have a concept of a bus-level "reset" operation?

No, it does not.  Most I2C devices don't even have a reset pin.  In a
reset situation in real hardware, the operation would be aborted by
the lines drifting high after the bus master has been reset.

So I think this is fine as is.

-corey

> 
> > +
> > +static void i2c_bus_class_init(ObjectClass *klass, void *data)
> > +{
> > +    ResettableClass *rc = RESETTABLE_CLASS(klass);
> > +    rc->phases.hold = i2c_bus_hold_reset;
> > +}
> > +
> >  static const TypeInfo i2c_bus_info = {
> >      .name = TYPE_I2C_BUS,
> >      .parent = TYPE_BUS,
> >      .instance_size = sizeof(I2CBus),
> > +    .class_init = i2c_bus_class_init,
> >  };
> 
> 
> 
> >  static int i2c_bus_pre_save(void *opaque)
> > diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
> > index 2a3abacd1b..49580e30e2 100644
> > --- a/include/hw/i2c/i2c.h
> > +++ b/include/hw/i2c/i2c.h
> > @@ -64,7 +64,7 @@ struct I2CSlave {
> >  };
> >
> >  #define TYPE_I2C_BUS "i2c-bus"
> > -OBJECT_DECLARE_SIMPLE_TYPE(I2CBus, I2C_BUS)
> > +OBJECT_DECLARE_TYPE(I2CBus, I2CBusClass, I2C_BUS)
> 
> I don't think you need this change any more ?
> 
> thanks
> -- PMM
> 

Re: [PATCH v3 1/3] hw/i2c: core: Add reset

[Joe Komlodi]

On Fri, Feb 16, 2024 at 5:04 PM Corey Minyard <minyard@acm.org> wrote:
>
> On Thu, Feb 08, 2024 at 04:39:10PM +0000, Peter Maydell wrote:
> > On Fri, 2 Feb 2024 at 20:48, Joe Komlodi <komlodi@google.com> wrote:
> > >
> > > It's possible for a reset to come in the middle of a transaction, which
> > > causes the bus to be in an old state when a new transaction comes in.
> > >
> > > Signed-off-by: Joe Komlodi <komlodi@google.com>
> > > ---
> > >  hw/i2c/core.c        | 19 +++++++++++++++++++
> > >  include/hw/i2c/i2c.h |  2 +-
> > >  2 files changed, 20 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/hw/i2c/core.c b/hw/i2c/core.c
> > > index 4cf30b2c86..3128067bba 100644
> > > --- a/hw/i2c/core.c
> > > +++ b/hw/i2c/core.c
> > > @@ -23,10 +23,29 @@ static Property i2c_props[] = {
> > >      DEFINE_PROP_END_OF_LIST(),
> > >  };
> > >
> > > +static void i2c_bus_hold_reset(Object *obj)
> > > +{
> > > +    I2CBus *bus = I2C_BUS(obj);
> > > +    I2CNode *node, *next;
> > > +
> > > +    bus->broadcast = false;
> > > +    QLIST_FOREACH_SAFE(node, &bus->current_devs, next, next) {
> > > +        QLIST_REMOVE(node, next);
> > > +        g_free(node);
> > > +    }
> > > +}
> >
> > This does what it says it's going to do; but I think it
> > would be good to hear from Corey whether it's better to
> > do this, or instead to call i2c_end_transfer() in the
> > reset-enter phase.
>
> Sorry, I missed this, I'm having major chaos going on right now in my
> life.

No worries! I also missed this for a bit.
>
> I don't think i2c_end_transfer() is the right thing to do.  The transfer
> has not cleanly ended, it is just forgotten.

Sounds good to me, I'll send up v4 with the change Peter pointed out.

Thanks,
Joe

>
> >
> > Mostly QEMU's "reset" is like power-cycling, in which case
> > I guess that what we have here where we just forget about
> > the in-progress transfer and assume the device on the other
> > end is also going to reset back to a neutral state is what
> > we want.
> >
> > Does i2c have a concept of a bus-level "reset" operation?
>
> No, it does not.  Most I2C devices don't even have a reset pin.  In a
> reset situation in real hardware, the operation would be aborted by
> the lines drifting high after the bus master has been reset.
>
> So I think this is fine as is.
>
> -corey
>
> >
> > > +
> > > +static void i2c_bus_class_init(ObjectClass *klass, void *data)
> > > +{
> > > +    ResettableClass *rc = RESETTABLE_CLASS(klass);
> > > +    rc->phases.hold = i2c_bus_hold_reset;
> > > +}
> > > +
> > >  static const TypeInfo i2c_bus_info = {
> > >      .name = TYPE_I2C_BUS,
> > >      .parent = TYPE_BUS,
> > >      .instance_size = sizeof(I2CBus),
> > > +    .class_init = i2c_bus_class_init,
> > >  };
> >
> >
> >
> > >  static int i2c_bus_pre_save(void *opaque)
> > > diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
> > > index 2a3abacd1b..49580e30e2 100644
> > > --- a/include/hw/i2c/i2c.h
> > > +++ b/include/hw/i2c/i2c.h
> > > @@ -64,7 +64,7 @@ struct I2CSlave {
> > >  };
> > >
> > >  #define TYPE_I2C_BUS "i2c-bus"
> > > -OBJECT_DECLARE_SIMPLE_TYPE(I2CBus, I2C_BUS)
> > > +OBJECT_DECLARE_TYPE(I2CBus, I2CBusClass, I2C_BUS)
> >
> > I don't think you need this change any more ?
> >
> > thanks
> > -- PMM
> >

[PATCH v3 2/3] hw/i2c/smbus_slave: Add object path on error prints

[Joe Komlodi]

The current logging doesn't tell us which specific smbus device is an
error state.

Signed-off-by: Joe Komlodi <komlodi@google.com>
---
 hw/i2c/smbus_slave.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c
index 1300c9ec72..9f9afc25a4 100644
--- a/hw/i2c/smbus_slave.c
+++ b/hw/i2c/smbus_slave.c
@@ -25,11 +25,15 @@
 #define DPRINTF(fmt, ...) \
 do { printf("smbus(%02x): " fmt , dev->i2c.address, ## __VA_ARGS__); } while (0)
 #define BADF(fmt, ...) \
-do { fprintf(stderr, "smbus: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
+do { g_autofree char *qom_path = object_get_canonical_path(OBJECT(dev));  \
+    fprintf(stderr, "%s: smbus: error: " fmt , qom_path, ## __VA_ARGS__); \
+            exit(1); } while (0)
 #else
 #define DPRINTF(fmt, ...) do {} while(0)
 #define BADF(fmt, ...) \
-do { fprintf(stderr, "smbus: error: " fmt , ## __VA_ARGS__);} while (0)
+do { g_autofree char *qom_path = object_get_canonical_path(OBJECT(dev));  \
+    fprintf(stderr, "%s: smbus: error: " fmt , qom_path, ## __VA_ARGS__); \
+             } while (0)
 #endif
 
 enum {
-- 
2.43.0.594.gd9cf4e227d-goog

Re: [PATCH v3 2/3] hw/i2c/smbus_slave: Add object path on error prints

[Peter Maydell]

On Fri, 2 Feb 2024 at 20:48, Joe Komlodi <komlodi@google.com> wrote:
>
> The current logging doesn't tell us which specific smbus device is an
> error state.
>
> Signed-off-by: Joe Komlodi <komlodi@google.com>
> ---

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

[PATCH v3 3/3] hw/i2c: smbus_slave: Reset state on reset

[Joe Komlodi]

If a reset comes while the SMBus device is not in its idle state, it's
possible for it to get confused on valid transactions post-reset.

Signed-off-by: Joe Komlodi <komlodi@google.com>
---
 hw/i2c/smbus_slave.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c
index 9f9afc25a4..4615e8b097 100644
--- a/hw/i2c/smbus_slave.c
+++ b/hw/i2c/smbus_slave.c
@@ -201,10 +201,19 @@ static int smbus_i2c_send(I2CSlave *s, uint8_t data)
     return 0;
 }
 
+static void smbus_device_hold_reset(Object *obj)
+{
+    SMBusDevice *dev = SMBUS_DEVICE(obj);
+    dev->mode = SMBUS_IDLE;
+    dev->data_len = 0;
+}
+
 static void smbus_device_class_init(ObjectClass *klass, void *data)
 {
     I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
+    rc->phases.hold = smbus_device_hold_reset;
     sc->event = smbus_i2c_event;
     sc->recv = smbus_i2c_recv;
     sc->send = smbus_i2c_send;
-- 
2.43.0.594.gd9cf4e227d-goog

Re: [PATCH v3 3/3] hw/i2c: smbus_slave: Reset state on reset

[Peter Maydell]

On Fri, 2 Feb 2024 at 20:48, Joe Komlodi <komlodi@google.com> wrote:
>
> If a reset comes while the SMBus device is not in its idle state, it's
> possible for it to get confused on valid transactions post-reset.
>
> Signed-off-by: Joe Komlodi <komlodi@google.com>
> ---
>  hw/i2c/smbus_slave.c | 9 +++++++++
>  1 file changed, 9 insertions(+)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM