From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34782) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cCQ54-0000Q3-TX for qemu-devel@nongnu.org; Thu, 01 Dec 2016 07:03:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cCQ54-0003fu-7h for qemu-devel@nongnu.org; Thu, 01 Dec 2016 07:03:14 -0500 Received: from mail-vk0-x22b.google.com ([2607:f8b0:400c:c05::22b]:33686) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cCQ53-0003ff-Ru for qemu-devel@nongnu.org; Thu, 01 Dec 2016 07:03:14 -0500 Received: by mail-vk0-x22b.google.com with SMTP id 137so127149281vkl.0 for ; Thu, 01 Dec 2016 04:03:13 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <369668b9-d158-45dd-562d-cf25cdaaa749@arm.com> References: <1480569402-8848-1-git-send-email-wei@redhat.com> <1480569402-8848-3-git-send-email-wei@redhat.com> <20161201090303.6vdo7iqlj2lfqqvv@kamzik.brq.redhat.com> <369668b9-d158-45dd-562d-cf25cdaaa749@arm.com> From: Peter Maydell Date: Thu, 1 Dec 2016 12:02:52 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [kvm-unit-tests PATCH v13 2/4] arm: Add PMU test List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Andre Przywara Cc: Andrew Jones , Wei Huang , Aaron Lindsay , kvm-devel , croberts@codeaurora.org, QEMU Developers , Alistair Francis , "kvmarm@lists.cs.columbia.edu" , Shannon Zhao On 1 December 2016 at 11:28, Andre Przywara wrote: > I don't think so. At least here as a _variable_ type uint32_t is > probably the right one, as the ARMv8 ARM explicitly says that PMCR is a > 32-bit register, for both bitnesses. For 64-bit ARM this is strictly speaking just shorthand for "64-bit register with the top 32-bit being RES0". It is in theory possible that a future architecture extension might define uses for those RES0 bits. thanks -- PMM