From: Peter Maydell <peter.maydell@linaro.org>
To: Palmer Dabbelt <palmer@sifive.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
QEMU Developers <qemu-devel@nongnu.org>,
Fabien Chouteau <chouteau@adacore.com>
Subject: Re: [Qemu-devel] [PULL 01/29] SiFive RISC-V GPIO Device
Date: Thu, 30 May 2019 11:57:12 +0100 [thread overview]
Message-ID: <CAFEAcA-01sahAvfLRoe3e9RfCcgmk4+Ubceufg9hhmwQAFpbRQ@mail.gmail.com> (raw)
In-Reply-To: <20190526010948.3923-2-palmer@sifive.com>
On Sun, 26 May 2019 at 02:10, Palmer Dabbelt <palmer@sifive.com> wrote:
>
> From: Fabien Chouteau <chouteau@adacore.com>
>
> QEMU model of the GPIO device on the SiFive E300 series SOCs.
>
> The pins are not used by a board definition yet, however this
> implementation can already be used to trigger GPIO interrupts from the
> software by configuring a pin as both output and input.
>
> Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
> Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Hi; this patch causes Coverity to complain about a memory
leak (CID 1401707):
> static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
> {
> const struct MemmapEntry *memmap = sifive_e_memmap;
> + Error *err = NULL;
>
> SiFiveESoCState *s = RISCV_E_SOC(dev);
> MemoryRegion *sys_mem = get_system_memory();
> @@ -184,8 +188,28 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
> sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
> memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
> sifive_prci_create(memmap[SIFIVE_E_PRCI].base);
> - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.gpio0",
> - memmap[SIFIVE_E_GPIO0].base, memmap[SIFIVE_E_GPIO0].size);
> +
> + /* GPIO */
> +
> + object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
This function allocated xip_mem and mask_rom via g_new() but
then this error-exit doesn't free them.
The best way to fix this is to stop doing separate memory
allocations at all -- instead just have fields in the
SiFiveESoCState struct
MemoryRegion xip_mem;
Memory_Region mask_rom;
and pass &s->xip_mem etc where currently the code uses xip_mem.
thanks
-- PMM
next prev parent reply other threads:[~2019-05-30 10:58 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-26 1:09 [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1 Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 01/29] SiFive RISC-V GPIO Device Palmer Dabbelt
2019-05-30 10:57 ` Peter Maydell [this message]
2019-06-14 12:10 ` Palmer Dabbelt
2019-06-17 8:46 ` Fabien Chouteau
2019-05-26 1:09 ` [Qemu-devel] [PULL 02/29] target/riscv: Do not allow sfence.vma from user mode Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 03/29] RISC-V: fix single stepping over ret and other branching instructions Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 04/29] target/riscv: Name the argument sets for all of insn32 formats Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 05/29] target/riscv: Use --static-decode for decodetree Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 06/29] target/riscv: Merge argument sets for insn32 and insn16 Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 07/29] target/riscv: Merge argument decode for RVC shifti Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 08/29] target/riscv: Use pattern groups in insn16.decode Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 09/29] target/riscv: Split RVC32 and RVC64 insns into separate files Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 10/29] target/riscv: Split gen_arith_imm into functional and temp Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 11/29] target/riscv: Remove spaces from register names Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 12/29] target/riscv: Remove unused include of riscv_htif.h for virt board riscv Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 13/29] linux-user/riscv: Add the CPU type as a comment Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 14/29] riscv: virt: Allow specifying a CPU via commandline Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 15/29] target/riscv: Create settable CPU properties Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 16/29] target/riscv: Add a base 32 and 64 bit CPU Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 17/29] target/riscv: Deprecate the generic no MMU CPUs Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 18/29] riscv: spike: Add a generic spike machine Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 19/29] target/riscv: Mark privilege level 2 as reserved Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 20/29] target/riscv: Trigger interrupt on MIP update asynchronously Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 21/29] target/riscv: Improve the scause logic Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 22/29] target/riscv: Add the MPV and MTL mstatus bits Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 23/29] target/riscv: Allow setting mstatus virtulisation bits Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 24/29] target/riscv: Add Hypervisor CSR macros Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 25/29] target/riscv: Add the HSTATUS register masks Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 26/29] target/riscv: Add the HGATP " Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 27/29] target/riscv: Add checks for several RVC reserved operands Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 28/29] target/riscv: More accurate handling of `sip` CSR Palmer Dabbelt
2019-05-26 1:09 ` [Qemu-devel] [PULL 29/29] target/riscv: Only flush TLB if SATP.ASID changes Palmer Dabbelt
2019-05-28 11:25 ` [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1 Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAFEAcA-01sahAvfLRoe3e9RfCcgmk4+Ubceufg9hhmwQAFpbRQ@mail.gmail.com \
--to=peter.maydell@linaro.org \
--cc=chouteau@adacore.com \
--cc=palmer@sifive.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).