From: Peter Maydell <peter.maydell@linaro.org>
To: "Alex Bennée" <alex.bennee@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>,
QEMU Developers <qemu-devel@nongnu.org>,
"patches@linaro.org" <patches@linaro.org>
Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH] nvic: Fix ARMv7M MPU_RBAR reads
Date: Mon, 6 Nov 2017 16:34:59 +0000 [thread overview]
Message-ID: <CAFEAcA-02WxVWayj=ZZS9Wq+6herJm2=jdKbfDAV1iYMvLUTBA@mail.gmail.com> (raw)
In-Reply-To: <871slbs7iv.fsf@linaro.org>
On 6 November 2017 at 16:20, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Peter Maydell <peter.maydell@linaro.org> writes:
>
>> Fix an incorrect mask expression in the handling of v7M MPU_RBAR
>> reads that meant that we would always report the ADDR field as zero.
>
> nit: you could extend that to: "..as zero because we mask it when
> written".
The ADDR field is bits [31:5], so it's true even if we don't
mask on writes.
thanks
-- PMM
prev parent reply other threads:[~2017-11-06 16:35 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-03 18:13 [Qemu-devel] [PATCH] nvic: Fix ARMv7M MPU_RBAR reads Peter Maydell
2017-11-06 16:20 ` [Qemu-devel] [Qemu-arm] " Alex Bennée
2017-11-06 16:34 ` Peter Maydell [this message]
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