* [Qemu-devel] [PATCH] nvic: Fix ARMv7M MPU_RBAR reads
@ 2017-11-03 18:13 Peter Maydell
2017-11-06 16:20 ` [Qemu-devel] [Qemu-arm] " Alex Bennée
0 siblings, 1 reply; 3+ messages in thread
From: Peter Maydell @ 2017-11-03 18:13 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: patches
Fix an incorrect mask expression in the handling of v7M MPU_RBAR
reads that meant that we would always report the ADDR field as zero.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
Doesn't affect v8M, which is a different codepath.
hw/intc/armv7m_nvic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index be46639..5d9c883 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -977,7 +977,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
if (region >= cpu->pmsav7_dregion) {
return 0;
}
- return (cpu->env.pmsav7.drbar[region] & 0x1f) | (region & 0xf);
+ return (cpu->env.pmsav7.drbar[region] & ~0x1f) | (region & 0xf);
}
case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */
case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [Qemu-devel] [Qemu-arm] [PATCH] nvic: Fix ARMv7M MPU_RBAR reads
2017-11-03 18:13 [Qemu-devel] [PATCH] nvic: Fix ARMv7M MPU_RBAR reads Peter Maydell
@ 2017-11-06 16:20 ` Alex Bennée
2017-11-06 16:34 ` Peter Maydell
0 siblings, 1 reply; 3+ messages in thread
From: Alex Bennée @ 2017-11-06 16:20 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, qemu-devel, patches
Peter Maydell <peter.maydell@linaro.org> writes:
> Fix an incorrect mask expression in the handling of v7M MPU_RBAR
> reads that meant that we would always report the ADDR field as zero.
nit: you could extend that to: "..as zero because we mask it when
written".
As I see you do:
cpu->env.pmsav7.drbar[region] = value & ~0x1f;
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> Doesn't affect v8M, which is a different codepath.
>
> hw/intc/armv7m_nvic.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
> index be46639..5d9c883 100644
> --- a/hw/intc/armv7m_nvic.c
> +++ b/hw/intc/armv7m_nvic.c
> @@ -977,7 +977,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
> if (region >= cpu->pmsav7_dregion) {
> return 0;
> }
> - return (cpu->env.pmsav7.drbar[region] & 0x1f) | (region & 0xf);
> + return (cpu->env.pmsav7.drbar[region] & ~0x1f) | (region & 0xf);
> }
> case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */
> case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */
--
Alex Bennée
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [Qemu-devel] [Qemu-arm] [PATCH] nvic: Fix ARMv7M MPU_RBAR reads
2017-11-06 16:20 ` [Qemu-devel] [Qemu-arm] " Alex Bennée
@ 2017-11-06 16:34 ` Peter Maydell
0 siblings, 0 replies; 3+ messages in thread
From: Peter Maydell @ 2017-11-06 16:34 UTC (permalink / raw)
To: Alex Bennée; +Cc: qemu-arm, QEMU Developers, patches@linaro.org
On 6 November 2017 at 16:20, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Peter Maydell <peter.maydell@linaro.org> writes:
>
>> Fix an incorrect mask expression in the handling of v7M MPU_RBAR
>> reads that meant that we would always report the ADDR field as zero.
>
> nit: you could extend that to: "..as zero because we mask it when
> written".
The ADDR field is bits [31:5], so it's true even if we don't
mask on writes.
thanks
-- PMM
^ permalink raw reply [flat|nested] 3+ messages in thread
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2017-11-03 18:13 [Qemu-devel] [PATCH] nvic: Fix ARMv7M MPU_RBAR reads Peter Maydell
2017-11-06 16:20 ` [Qemu-devel] [Qemu-arm] " Alex Bennée
2017-11-06 16:34 ` Peter Maydell
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