From: Peter Maydell <peter.maydell@linaro.org>
To: eric.auger@redhat.com
Cc: eric.auger.pro@gmail.com, richard.henderson@linaro.org,
pbonzini@redhat.com, qemu-devel@nongnu.org, philmd@linaro.org
Subject: Re: [PATCH v2] target/arm: Add raw_writes ops for register whose write induce TLB maintenance
Date: Thu, 16 Feb 2023 17:23:19 +0000 [thread overview]
Message-ID: <CAFEAcA-06ogbs-m-5b3SUfAC2qkRFri0yxsY68ogA70mwrXErA@mail.gmail.com> (raw)
In-Reply-To: <e537087d-a8ab-f30b-aeff-76750966a08b@redhat.com>
On Thu, 16 Feb 2023 at 17:06, Eric Auger <eric.auger@redhat.com> wrote:
>
> Hi Peter,
>
> On 2/16/23 14:51, Peter Maydell wrote:
> > On Mon, 13 Feb 2023 at 18:38, Eric Auger <eric.auger@redhat.com> wrote:
> >> Some registers whose 'cooked' writefns induce TLB maintenance do
> >> not have raw_writefn ops defined. If only the writefn ops is set
> >> (ie. no raw_writefn is provided), it is assumed the cooked also
> >> work as the raw one. For those registers it is not obvious the
> >> tlb_flush works on KVM mode so better/safer setting the raw write.
> >>
> >> Signed-off-by: Eric Auger <eric.auger@redhat.com>
> >> Suggested-by: Peter Maydell <peter.maydell@linaro.org>
> >> { .name = "HCR", .state = ARM_CP_STATE_AA32,
> >> .type = ARM_CP_ALIAS | ARM_CP_IO,
> >> .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
> >> .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
> >> - .writefn = hcr_writelow },
> >> + .writefn = hcr_writelow, .raw_writefn = raw_write },
> > This is going to do the wrong thing on big-endian hosts, because
> > the data value is the low 32 bits and the raw_writefn will
> > write that to the whole 64-bit value. We could implement a
> > special purpose raw write for this register which just writes
> > the value to the low 32 bits, I guess.
> >
> > For KVM we could ignore this, though -- the register is EL2 only,
> > and also is ARM_CP_ALIAS, which means we won't try to do anything
> > with it for the KVM<->QEMU state sync or the migration codepaths.
> OK so can I simply revert that change.
Yes, that seems easiest.
> >> @@ -6139,7 +6145,7 @@ static const ARMCPRegInfo el2_v8_cp_reginfo[] = {
> >> .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
> >> .access = PL2_RW,
> >> .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2),
> >> - .writefn = hcr_writehigh },
> >> + .writefn = hcr_writehigh, .raw_writefn = raw_write },
> > Similarly this would need a special purpose raw write function
> > since we want to only touch the high 32 bits; and again for
> > the KVM case we won't ever be doing a raw access to this register.
>
> same question: can I simply revert that change?
Ditto.
-- PMM
prev parent reply other threads:[~2023-02-16 17:23 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-13 18:38 [PATCH v2] target/arm: Add raw_writes ops for register whose write induce TLB maintenance Eric Auger
2023-02-16 13:51 ` Peter Maydell
2023-02-16 17:06 ` Eric Auger
2023-02-16 17:23 ` Peter Maydell [this message]
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