From: Peter Maydell <peter.maydell@linaro.org>
To: Greg Bellows <greg.bellows@linaro.org>
Cc: Sergey Fedorov <serge.fdrv@gmail.com>,
QEMU Developers <qemu-devel@nongnu.org>,
Fabian Aggeler <aggelerf@ethz.ch>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Subject: Re: [Qemu-devel] [PATCH v8 12/27] target-arm: add MVBAR support
Date: Fri, 31 Oct 2014 13:35:51 +0000 [thread overview]
Message-ID: <CAFEAcA-2sQ4eD64j_fo-7U_xWxDjzMSKfQsiz6ukoQZ7g0b1dA@mail.gmail.com> (raw)
In-Reply-To: <1414704538-17103-13-git-send-email-greg.bellows@linaro.org>
On 30 October 2014 21:28, Greg Bellows <greg.bellows@linaro.org> wrote:
> From: Fabian Aggeler <aggelerf@ethz.ch>
>
> Use MVBAR register as exception vector base address for
> exceptions taken to CPU monitor mode.
>
> Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com>
> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
> Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
If you put the cp/opc fields in the right order, then
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
(I shan't mention field ordering again but you can assume
it applies to all the other patches in this series too.)
thanks
-- PMM
next prev parent reply other threads:[~2014-10-31 15:01 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-30 21:28 [Qemu-devel] [PATCH v8 00/27] target-arm: add Security Extensions for CPUs Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 01/27] target-arm: extend async excp masking Greg Bellows
2014-10-31 19:00 ` Peter Maydell
2014-11-05 21:12 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 02/27] target-arm: add async excp target_el function Greg Bellows
2014-10-31 11:56 ` Peter Maydell
2014-10-31 14:14 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 03/27] target-arm: add banked register accessors Greg Bellows
2014-10-31 16:50 ` Peter Maydell
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 04/27] target-arm: add non-secure Translation Block flag Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 05/27] target-arm: add CPREG secure state support Greg Bellows
2014-10-31 12:15 ` Peter Maydell
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 06/27] target-arm: add secure state bit to CPREG hash Greg Bellows
2014-10-31 12:28 ` Peter Maydell
2014-10-31 12:31 ` Peter Maydell
2014-10-31 16:20 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 07/27] target-arm: insert AArch32 cpregs twice into hashtable Greg Bellows
2014-10-31 12:44 ` Peter Maydell
2014-10-31 19:01 ` Greg Bellows
2014-11-04 22:20 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 08/27] target-arm: move AArch32 SCR into security reglist Greg Bellows
2014-10-31 12:06 ` Peter Maydell
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 09/27] target-arm: implement IRQ/FIQ routing to Monitor mode Greg Bellows
2014-10-31 12:01 ` Peter Maydell
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 10/27] target-arm: add NSACR register Greg Bellows
2014-10-31 13:24 ` Peter Maydell
2014-10-31 21:09 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 11/27] target-arm: add SDER definition Greg Bellows
2014-10-31 13:30 ` Peter Maydell
2014-10-31 21:17 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 12/27] target-arm: add MVBAR support Greg Bellows
2014-10-31 13:35 ` Peter Maydell [this message]
2014-10-31 21:19 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 13/27] target-arm: add SCTLR_EL3 and make SCTLR banked Greg Bellows
2014-10-31 14:07 ` Peter Maydell
2014-10-31 21:51 ` Greg Bellows
2014-10-31 23:26 ` Peter Maydell
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 14/27] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI Greg Bellows
2014-10-31 14:18 ` Peter Maydell
2014-11-03 14:57 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 15/27] target-arm: make CSSELR banked Greg Bellows
2014-10-31 14:23 ` Peter Maydell
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 16/27] target-arm: add TTBR0_EL3 and make TTBR0/1 banked Greg Bellows
2014-10-31 15:04 ` Peter Maydell
2014-11-04 22:44 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 17/27] target-arm: add TCR_EL3 and make TTBCR banked Greg Bellows
2014-10-31 15:07 ` Peter Maydell
2014-11-04 22:45 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 18/27] target-arm: make c2_mask and c2_base_mask banked Greg Bellows
2014-10-31 15:26 ` Peter Maydell
2014-11-04 22:46 ` Greg Bellows
2014-11-04 23:27 ` Peter Maydell
2014-11-05 15:09 ` Greg Bellows
2014-11-05 15:15 ` Peter Maydell
2014-11-05 15:18 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 19/27] target-arm: make DACR banked Greg Bellows
2014-10-31 15:38 ` Peter Maydell
2014-11-03 21:23 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 20/27] target-arm: make IFSR banked Greg Bellows
2014-10-31 16:18 ` Peter Maydell
2014-11-05 22:19 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 21/27] target-arm: make DFSR banked Greg Bellows
2014-10-31 16:19 ` Peter Maydell
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 22/27] target-arm: make IFAR/DFAR banked Greg Bellows
2014-10-31 16:24 ` Peter Maydell
2014-11-03 22:59 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 23/27] target-arm: make PAR banked Greg Bellows
2014-10-31 17:21 ` Peter Maydell
2014-11-03 22:58 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 24/27] target-arm: make VBAR banked Greg Bellows
2014-10-31 17:22 ` Peter Maydell
2014-11-03 22:06 ` Greg Bellows
2014-11-03 22:49 ` Peter Maydell
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 25/27] target-arm: make c13 cp regs banked (FCSEIDR, ...) Greg Bellows
2014-10-31 17:27 ` Peter Maydell
2014-11-03 22:57 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 26/27] target-arm: make MAIR0/1 banked Greg Bellows
2014-10-31 17:31 ` Peter Maydell
2014-11-03 23:00 ` Greg Bellows
2014-11-04 14:13 ` Greg Bellows
2014-10-30 21:28 ` [Qemu-devel] [PATCH v8 27/27] target-arm: add cpu feature EL3 to CPUs with Security Extensions Greg Bellows
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