From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:54493) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rd5pk-0000oa-6r for qemu-devel@nongnu.org; Tue, 20 Dec 2011 14:58:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rd5pi-0007ZE-8O for qemu-devel@nongnu.org; Tue, 20 Dec 2011 14:58:44 -0500 Received: from mail-qy0-f173.google.com ([209.85.216.173]:44423) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rd5pi-0007Yw-5u for qemu-devel@nongnu.org; Tue, 20 Dec 2011 14:58:42 -0500 Received: by qcsd15 with SMTP id d15so4294376qcs.4 for ; Tue, 20 Dec 2011 11:58:41 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <4EF0DDEB.40302@calxeda.com> References: <4EF0DDEB.40302@calxeda.com> Date: Tue, 20 Dec 2011 19:58:41 +0000 Message-ID: From: Peter Maydell Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 4/9] arm: add dummy gic security registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Mark Langsdorf Cc: qemu-devel@nongnu.org, paul@codesourcery.com On 20 December 2011 19:11, Mark Langsdorf wrot= e: > From: Rob Herring > > Signed-off-by: Rob Herring > Signed-off-by: Mark Langsdorf > --- > =C2=A0hw/arm_gic.c | =C2=A0 10 ++++++++-- > =C2=A01 files changed, 8 insertions(+), 2 deletions(-) > > diff --git a/hw/arm_gic.c b/hw/arm_gic.c > index 9b52119..5974c2f 100644 > --- a/hw/arm_gic.c > +++ b/hw/arm_gic.c > @@ -274,7 +274,7 @@ static uint32_t gic_dist_readb(void *opaque, > target_phys_addr_t offset) > > =C2=A0 =C2=A0 cpu =3D gic_get_current_cpu(); > =C2=A0 =C2=A0 cm =3D 1 << cpu; > - =C2=A0 =C2=A0if (offset < 0x100) { > + =C2=A0 =C2=A0if (offset < 0x80) { > =C2=A0#ifndef NVIC > =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (offset =3D=3D 0) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return s->enabled; > @@ -284,6 +284,9 @@ static uint32_t gic_dist_readb(void *opaque, > target_phys_addr_t offset) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return 0; > =C2=A0#endif > =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto bad_reg; > + =C2=A0 =C2=A0} else if (offset < 0x100) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Interrupt Security */ > + =C2=A0 =C2=A0 =C2=A0 =C2=A0return 0; This won't actually break anything, but really the handling of 0x80..0xff would be inside the first if() clause, because of the way we piggyback the v7M NVIC off these functions. (We should clean that up, really). Anyway, the v7M NVIC doesn't own 0x0..0xff, which is what the first if () clause is marking off. Ditto in the write function. It would also be nice to have the comment explicitly say that these registers are defined to RAZ/WI in GIC implementations that don't implement the security extensions. (Strictly speaking, in the 11MPcore GIC these locations are reserved and probably don't RAZ/WI, but I don't think we need to worry about that wrinkle now.) > =C2=A0 =C2=A0 } else if (offset < 0x200) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Interrupt Set/Clear Enable. =C2=A0*/ > =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (offset < 0x180) > @@ -404,7 +407,7 @@ static void gic_dist_writeb(void *opaque, > target_phys_addr_t offset, > =C2=A0 =C2=A0 int cpu; > > =C2=A0 =C2=A0 cpu =3D gic_get_current_cpu(); > - =C2=A0 =C2=A0if (offset < 0x100) { > + =C2=A0 =C2=A0if (offset < 0x80) { > =C2=A0#ifdef NVIC > =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto bad_reg; > =C2=A0#else > @@ -417,6 +420,9 @@ static void gic_dist_writeb(void *opaque, > target_phys_addr_t offset, > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto bad_reg; > =C2=A0 =C2=A0 =C2=A0 =C2=A0 } > =C2=A0#endif > + =C2=A0 =C2=A0} else if (offset < 0x100) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Interrupt Security Registers */ > + =C2=A0 =C2=A0 =C2=A0 =C2=A0/* ignore */ > =C2=A0 =C2=A0 } else if (offset < 0x180) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Interrupt Set Enable. =C2=A0*/ > =C2=A0 =C2=A0 =C2=A0 =C2=A0 irq =3D (offset - 0x100) * 8 + GIC_BASE_IRQ; > -- > 1.7.5.4 > -- PMM