From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51098) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0r3k-0007mu-US for qemu-devel@nongnu.org; Fri, 05 Jun 2015 08:49:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z0r3g-0005X9-Ty for qemu-devel@nongnu.org; Fri, 05 Jun 2015 08:49:16 -0400 Received: from mail-ie0-f170.google.com ([209.85.223.170]:36205) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0r3g-0005X3-QV for qemu-devel@nongnu.org; Fri, 05 Jun 2015 08:49:12 -0400 Received: by ieclw1 with SMTP id lw1so57141475iec.3 for ; Fri, 05 Jun 2015 05:49:12 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <5006DF1F5103294E8DA02CC4C71B1BF8085C0F1C@SESTOEX04.enea.se> References: <5006DF1F5103294E8DA02CC4C71B1BF8085C0F1C@SESTOEX04.enea.se> From: Peter Maydell Date: Fri, 5 Jun 2015 13:48:51 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH 1/1] arm_gic: gic_update should always update all cores. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Johan Karlsson Cc: "qemu-devel@nongnu.org" On 13 November 2014 at 17:08, Johan Karlsson wrote: > This patch fixes so that gic_update always updates all the cores with new pending irq states. > If the function returns early it is possible to get interrupts that has already been acknowledged. > > Signed-off-by: Johan Karlsson > > diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c > index 270ce05..f1641f5 100644 > --- a/hw/intc/arm_gic.c > +++ b/hw/intc/arm_gic.c > @@ -61,7 +61,7 @@ void gic_update(GICState *s) > s->current_pending[cpu] = 1023; > if (!s->enabled || !s->cpu_enabled[cpu]) { > qemu_irq_lower(s->parent_irq[cpu]); > - return; > + continue; > } > best_prio = 0x100; > best_irq = 1023; Oops, this dropped through the cracks of the review process, but Johan just pinged me on IRC about it. Applied to target-arm.next, thanks. -- PMM